NXP Semiconductors
MKE02Z2
2024.06.02
MKE02Z2 Freescale Microcontroller
CM0PLUS
r0p0
little
2
false
8
32
ACMP0
Analog comparator
ACMP
0x0
0x0
0x4
registers
n
ACMP0
16
INT_ACMP0
16
C0
ACMP Control Register 0
0x1
8
read-write
n
0x0
0x0
ACNSEL
ACMP Negative Input Select
0
2
read-write
00
External reference 0
#00
01
External reference 1
#01
10
External reference 2
#10
11
DAC output
#11
ACPSEL
ACMP Positive Input Select
4
2
read-write
00
External reference 0
#00
01
External reference 1
#01
10
External reference 2
#10
11
DAC output
#11
RESERVED
no description available
2
2
read-only
RESERVED
no description available
6
2
read-only
C1
ACMP Control Register 1
0x2
8
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
The DAC is disabled.
#0
1
The DAC is enabled.
#1
DACREF
DAC Reference Select
6
1
read-write
0
The DAC selects Bandgap as the reference.
#0
1
The DAC selects VDDA as the reference.
#1
DACVAL
DAC Output Level Selection
0
6
read-write
C2
ACMP Control Register 2
0x3
8
read-write
n
0x0
0x0
ACIPE
ACMP Input Pin Enable
0
3
read-write
0
The corresponding external analog input is not allowed.
#0
1
The corresponding external analog input is allowed.
#1
RESERVED
no description available
3
5
read-only
CS
ACMP Control and Status Register
0x0
8
read-write
n
0x0
0x0
ACE
Analog Comparator Enable
7
1
read-write
0
The ACMP is disabled.
#0
1
The ACMP is enabled.
#1
ACF
ACMP Interrupt Flag Bit
5
1
read-write
ACIE
ACMP Interrupt Enable
4
1
read-write
0
Disable the ACMP Interrupt.
#0
1
Enable the ACMP Interrupt.
#1
ACMOD
ACMP MOD
0
2
read-write
00
ACMP interrupt on output falling edge.
#00
01
ACMP interrupt on output rising edge.
#01
10
ACMP interrupt on output falling edge.
#10
11
ACMP interrupt on output falling or rising edge.
#11
ACO
ACMP Output
3
1
read-only
ACOPE
ACMP Output Pin Enable
2
1
read-write
0
ACMP output cannot be placed onto external pin.
#0
1
ACMP output can be placed onto external pin.
#1
HYST
Analog Comparator Hystersis Selection
6
1
read-write
0
20 mV.
#0
1
30 mV.
#1
ACMP1
Analog comparator
ACMP
0x0
0x0
0x4
registers
n
ACMP1
21
INT_ACMP1
21
C0
ACMP Control Register 0
0x1
8
read-write
n
0x0
0x0
ACNSEL
ACMP Negative Input Select
0
2
read-write
00
External reference 0
#00
01
External reference 1
#01
10
External reference 2
#10
11
DAC output
#11
ACPSEL
ACMP Positive Input Select
4
2
read-write
00
External reference 0
#00
01
External reference 1
#01
10
External reference 2
#10
11
DAC output
#11
RESERVED
no description available
2
2
read-only
RESERVED
no description available
6
2
read-only
C1
ACMP Control Register 1
0x2
8
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
The DAC is disabled.
#0
1
The DAC is enabled.
#1
DACREF
DAC Reference Select
6
1
read-write
0
The DAC selects Bandgap as the reference.
#0
1
The DAC selects VDDA as the reference.
#1
DACVAL
DAC Output Level Selection
0
6
read-write
C2
ACMP Control Register 2
0x3
8
read-write
n
0x0
0x0
ACIPE
ACMP Input Pin Enable
0
3
read-write
0
The corresponding external analog input is not allowed.
#0
1
The corresponding external analog input is allowed.
#1
RESERVED
no description available
3
5
read-only
CS
ACMP Control and Status Register
0x0
8
read-write
n
0x0
0x0
ACE
Analog Comparator Enable
7
1
read-write
0
The ACMP is disabled.
#0
1
The ACMP is enabled.
#1
ACF
ACMP Interrupt Flag Bit
5
1
read-write
ACIE
ACMP Interrupt Enable
4
1
read-write
0
Disable the ACMP Interrupt.
#0
1
Enable the ACMP Interrupt.
#1
ACMOD
ACMP MOD
0
2
read-write
00
ACMP interrupt on output falling edge.
#00
01
ACMP interrupt on output rising edge.
#01
10
ACMP interrupt on output falling edge.
#10
11
ACMP interrupt on output falling or rising edge.
#11
ACO
ACMP Output
3
1
read-only
ACOPE
ACMP Output Pin Enable
2
1
read-write
0
ACMP output cannot be placed onto external pin.
#0
1
ACMP output can be placed onto external pin.
#1
HYST
Analog Comparator Hystersis Selection
6
1
read-write
0
20 mV.
#0
1
30 mV.
#1
ADC
Analog-to-digital converter
ADC
0x0
0x0
0x1C
registers
n
0x0
0x1C
registers
n
ADC0
15
APCTL1
Pin Control 1 Register
0x18
32
read-write
n
0x0
0x0
ADPC
ADC Pin Control
0
32
read-write
0
ADx pin I/O control enabled.
#0
1
ADx pin I/O control disabled.
#1
CV
Compare Value Register
0x14
32
read-write
n
0x0
0x0
CV
Conversion Result[11:0]
0
12
read-write
RESERVED
no description available
12
20
read-only
R
Conversion Result Register
0x10
32
read-only
n
0x0
0x0
ADR
Conversion Result
0
12
read-only
RESERVED
no description available
12
20
read-only
SC1
Status and Control Register 1
0x0
32
read-write
n
0x0
0x0
ADCH
Input Channel Select
0
5
read-write
10110
Temperature Sensor
#10110
10111
Bandgap
#10111
11101
VREFH
#11101
11110
VREFL
#11110
11111
Module disabled Reset FIFO in FIFO mode.
#11111
ADCO
Continuous Conversion Enable
5
1
read-write
0
One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are triggered.
#0
1
Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered.
#1
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt disabled.
#0
1
Conversion complete interrupt enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion not completed.
#0
1
Conversion completed.
#1
RESERVED
no description available
8
24
read-only
SC2
Status and Control Register 2
0x4
32
read-write
n
0x0
0x0
ACFE
Compare Function Enable
5
1
read-write
0
Compare function disabled.
#0
1
Compare function enabled.
#1
ACFGT
Compare Function Greater Than Enable
4
1
read-write
0
Compare triggers when input is less than compare level.
#0
1
Compare triggers when input is greater than or equal to compare level.
#1
ADACT
Conversion Active
7
1
read-only
0
Conversion not in progress.
#0
1
Conversion in progress.
#1
ADTRG
Conversion Trigger Select
6
1
read-write
0
Software trigger selected.
#0
1
Hardware trigger selected.
#1
FEMPTY
Result FIFO empty
3
1
read-only
0
Indicates that ADC result FIFO have at least one valid new data.
#0
1
Indicates that ADC result FIFO have no valid new data.
#1
FFULL
Result FIFO full
2
1
read-only
0
Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO.
#0
1
Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action.
#1
REFSEL
Voltage Reference Selection
0
2
read-write
00
Default voltage reference pin pair (VREFH/VREFL).
#00
01
Analog supply pin pair (VDDA/VSSA).
#01
10
Reserved.
#10
11
Reserved - Selects default voltage reference (VREFH/VREFL) pin pair.
#11
RESERVED
no description available
8
24
read-only
SC3
Status and Control Register 3
0x8
32
read-write
n
0x0
0x0
ADICLK
Input Clock Select
0
2
read-write
00
Bus clock
#00
01
Bus clock divided by 2
#01
10
Alternate clock (ALTCLK)
#10
11
Asynchronous clock (ADACK)
#11
ADIV
Clock Divide Select
5
2
read-write
00
Divide ration = 1, and clock rate = Input clock.
#00
01
Divide ration = 2, and clock rate = Input clock * 2.
#01
10
Divide ration = 3, and clock rate = Input clock * 4.
#10
11
Divide ration = 4, and clock rate = Input clock * 8.
#11
ADLPC
Low-Power Configuration
7
1
read-write
0
High speed configuration.
#0
1
Low power configuration:The power is reduced at the expense of maximum clock speed.
#1
ADLSMP
Long Sample Time Configuration
4
1
read-write
0
Short sample time.
#0
1
Long sample time.
#1
MODE
Conversion Mode Selection
2
2
read-write
00
8-bit conversion (N = 8)
#00
01
10-bit conversion (N = 10)
#01
10
12-bit conversion (N = 12)
#10
11
Reserved
#11
RESERVED
no description available
8
24
read-only
SC4
Status and Control Register 4
0xC
32
read-write
n
0x0
0x0
ACFSEL
no description available
5
1
read-write
0
OR all of compare trigger.
#0
1
AND all of compare trigger.
#1
AFDEP
no description available
0
3
read-write
000
FIFO is disabled.
#000
001
2-level FIFO is enabled.
#001
010
3-level FIFO is enabled..
#010
011
4-level FIFO is enabled.
#011
100
5-level FIFO is enabled.
#100
101
6-level FIFO is enabled.
#101
110
7-level FIFO is enabled.
#110
111
8-level FIFO is enabled.
#111
ASCANE
FIFO Scan Mode Enable
6
1
read-write
0
FIFO scan mode disabled.
#0
1
FIFO scan mode enabled.
#1
RESERVED
no description available
3
2
read-only
RESERVED
no description available
7
25
read-only
CRC
Cyclic Redundancy Check
CRC
0x0
0x0
0xC
registers
n
CTRL
CRC Control register
0x8
32
read-write
n
0x0
0x0
FXOR
Complement Read Of CRC Data Register
26
1
read-write
0
No XOR on reading.
#0
1
Invert or complement the read value of the CRC Data register.
#1
RESERVED
no description available
0
24
read-only
RESERVED
no description available
27
1
read-only
TCRC
no description available
24
1
read-write
0
16-bit CRC protocol.
#0
1
32-bit CRC protocol.
#1
TOT
Type Of Transpose For Writes
30
2
read-write
00
No transposition.
#00
01
Bits in bytes are transposed; bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
TOTR
Type Of Transpose For Read
28
2
read-write
00
No transposition.
#00
01
Bits in bytes are transposed; bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
WAS
Write CRC Data Register As Seed
25
1
read-write
0
Writes to the CRC data register are data values.
#0
1
Writes to the CRC data register are seed values.
#1
CTRLHU
CRC_CTRLHU register.
0xB
8
read-write
n
0x0
0x0
FXOR
no description available
2
1
read-write
0
No XOR on reading.
#0
1
Invert or complement the read value of CRC data register.
#1
RESERVED
no description available
3
1
read-only
TCRC
no description available
0
1
read-write
0
16-bit CRC protocol.
#0
1
32-bit CRC protocol.
#1
TOT
no description available
6
2
read-write
00
No Transposition.
#00
01
Bits in bytes are transposed, bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
TOTR
no description available
4
2
read-write
00
No Transposition.
#00
01
Bits in bytes are transposed, bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
WAS
no description available
1
1
read-write
0
Writes to CRC data register are data values.
#0
1
Writes to CRC data reguster are seed values.
#1
DATA
CRC Data register
CRC
0x0
32
read-write
n
0x0
0x0
HL
CRC High Lower Byte
16
8
read-write
HU
CRC High Upper Byte
24
8
read-write
LL
CRC Low Lower Byte
0
8
read-write
LU
CRC Low Upper Byte
8
8
read-write
DATAH
CRC_DATAH register.
CRC
0x2
16
read-write
n
0x0
0x0
DATAH
DATAH stores the high 16 bits of the 16/32 bit CRC
0
16
read-write
DATAHL
CRC_DATAHL register.
CRC
0x2
8
read-write
n
0x0
0x0
DATAHL
DATAHL stores the third 8 bits of the 32 bit CRC
0
8
read-write
DATAHU
CRC_DATAHU register.
0x3
8
read-write
n
0x0
0x0
DATAHU
DATAHU stores the fourth 8 bits of the 32 bit CRC
0
8
read-write
DATAL
CRC_DATAL register.
CRC
0x0
16
read-write
n
0x0
0x0
DATAL
DATAL stores the lower 16 bits of the 16/32 bit CRC
0
16
read-write
DATALL
CRC_DATALL register.
CRC
0x0
8
read-write
n
0x0
0x0
DATALL
CRCLL stores the first 8 bits of the 32 bit DATA
0
8
read-write
DATALU
CRC_DATALU register.
0x1
8
read-write
n
0x0
0x0
DATALU
DATALL stores the second 8 bits of the 32 bit CRC
0
8
read-write
GPOLY
CRC Polynomial register
CRC
0x4
32
read-write
n
0x0
0x0
HIGH
High Polynominal Half-word
16
16
read-write
LOW
Low Polynominal Half-word
0
16
read-write
GPOLYH
CRC_GPOLYH register.
CRC
0x6
16
read-write
n
0x0
0x0
GPOLYH
POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
0
16
read-write
GPOLYHL
CRC_GPOLYHL register.
CRC
0x6
8
read-write
n
0x0
0x0
GPOLYHL
POLYHL stores the third 8 bits of the 32 bit CRC
0
8
read-write
GPOLYHU
CRC_GPOLYHU register.
0x7
8
read-write
n
0x0
0x0
GPOLYHU
POLYHU stores the fourth 8 bits of the 32 bit CRC
0
8
read-write
GPOLYL
CRC_GPOLYL register.
CRC
0x4
16
read-write
n
0x0
0x0
GPOLYL
POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
0
16
read-write
GPOLYLL
CRC_GPOLYLL register.
CRC
0x4
8
read-write
n
0x0
0x0
GPOLYLL
POLYLL stores the first 8 bits of the 32 bit CRC
0
8
read-write
GPOLYLU
CRC_GPOLYLU register.
0x5
8
read-write
n
0x0
0x0
GPOLYLU
POLYLL stores the second 8 bits of the 32 bit CRC
0
8
read-write
FGPIOA
General Purpose Input/Output
FGPIO
0x0
0x0
0x1C
registers
n
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FGPIOB
General Purpose Input/Output
FGPIO
0x0
0x0
0x1C
registers
n
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FPTA
General Purpose Input/Output
FGPIO
0x0
0x0
0x1C
registers
n
FGPIOA_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
FGPIOA_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
FGPIOA_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
FGPIOA_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
FGPIOA_PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
FGPIOA_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
FGPIOA_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FPTB
General Purpose Input/Output
FGPIO
0x0
0x0
0x1C
registers
n
FGPIOB_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
FGPIOB_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
FGPIOB_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
FGPIOB_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
FGPIOB_PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
FGPIOB_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
FGPIOB_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
FTM0
FlexTimer Module
FTM
0x0
0x0
0x1C
registers
n
0x0
0x9C
registers
n
FTM0
17
INT_FTM0
17
C0SC
Channel (n) Status And Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status And Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
16
read-write
RESERVED
no description available
16
16
read-only
CNTIN
Counter Initial Value
0x4C
32
read-write
n
0x0
0x0
INIT
no description available
0
16
read-write
RESERVED
no description available
16
16
read-write
COMBINE
Function For Linked Channels
0x64
32
read-write
n
0x0
0x0
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
RESERVED
no description available
7
1
read-only
RESERVED
no description available
15
1
read-only
RESERVED
no description available
23
1
read-only
RESERVED
no description available
31
1
read-only
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
NUMTOF
TOF Frequency
0
5
read-write
RESERVED
no description available
5
1
read-only
RESERVED
no description available
8
1
read-only
RESERVED
no description available
11
21
read-only
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
n
0x0
0x0
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
DTVAL
Deadtime Value
0
6
read-write
RESERVED
no description available
8
24
read-only
EXTTRIG
FTM External Trigger
0x6C
32
read-write
n
0x0
0x0
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
RESERVED
no description available
8
24
read-write
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
n
0x0
0x0
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
RESERVED
no description available
16
16
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
n
0x0
0x0
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
RESERVED
no description available
12
20
read-only
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
n
0x0
0x0
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
RESERVED
no description available
4
28
read-only
FMS
Fault Mode Status
0x74
32
read-write
n
0x0
0x0
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
RESERVED
no description available
4
1
read-only
RESERVED
no description available
8
24
read-only
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
n
0x0
0x0
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
RESERVED
no description available
4
28
read-only
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
no description available
0
16
read-write
RESERVED
no description available
16
16
read-write
MODE
Features Mode Selection
0x54
32
read-write
n
0x0
0x0
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
RESERVED
no description available
8
24
read-only
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
n
0x0
0x0
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
RESERVED
no description available
8
24
read-only
OUTMASK
Output Mask
0x60
32
read-write
n
0x0
0x0
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
RESERVED
no description available
8
24
read-only
POL
Channels Polarity
0x70
32
read-write
n
0x0
0x0
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
RESERVED
no description available
8
24
read-write
PWMLOAD
FTM PWM Load
0x98
32
read-write
n
0x0
0x0
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
RESERVED
no description available
8
1
read-only
RESERVED
no description available
10
22
read-only
SC
Status And Control
0x0
32
read-write
n
0x0
0x0
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
RESERVED
no description available
8
24
read-only
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture And Compare Status
0x50
32
read-only
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
RESERVED
no description available
8
24
read-only
SWOCTRL
FTM Software Output Control
0x94
32
read-write
n
0x0
0x0
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
RESERVED
no description available
16
16
read-only
SYNC
Synchronization
0x58
32
read-write
n
0x0
0x0
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
RESERVED
no description available
8
24
read-only
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
n
0x0
0x0
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
HWINVC
no description available
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWOM
no description available
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWRSTCNT
no description available
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWSOC
no description available
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
HWWRBUF
no description available
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
RESERVED
no description available
1
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
13
3
read-only
RESERVED
no description available
21
11
read-only
SWINVC
no description available
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOM
no description available
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWRSTCNT
no description available
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWSOC
no description available
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
SWWRBUF
no description available
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
FTM1
FlexTimer Module
FTM
0x0
0x0
0x1C
registers
n
0x0
0x9C
registers
n
FTM1
18
INT_FTM1
18
C0SC
Channel (n) Status And Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status And Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
16
read-write
RESERVED
no description available
16
16
read-only
CNTIN
Counter Initial Value
0x4C
32
read-write
n
0x0
0x0
INIT
no description available
0
16
read-write
RESERVED
no description available
16
16
read-write
COMBINE
Function For Linked Channels
0x64
32
read-write
n
0x0
0x0
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
RESERVED
no description available
7
1
read-only
RESERVED
no description available
15
1
read-only
RESERVED
no description available
23
1
read-only
RESERVED
no description available
31
1
read-only
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
NUMTOF
TOF Frequency
0
5
read-write
RESERVED
no description available
5
1
read-only
RESERVED
no description available
8
1
read-only
RESERVED
no description available
11
21
read-only
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
n
0x0
0x0
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
DTVAL
Deadtime Value
0
6
read-write
RESERVED
no description available
8
24
read-only
EXTTRIG
FTM External Trigger
0x6C
32
read-write
n
0x0
0x0
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
RESERVED
no description available
8
24
read-write
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
n
0x0
0x0
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
RESERVED
no description available
16
16
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
n
0x0
0x0
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
RESERVED
no description available
12
20
read-only
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
n
0x0
0x0
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
RESERVED
no description available
4
28
read-only
FMS
Fault Mode Status
0x74
32
read-write
n
0x0
0x0
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
RESERVED
no description available
4
1
read-only
RESERVED
no description available
8
24
read-only
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
n
0x0
0x0
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
RESERVED
no description available
4
28
read-only
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
no description available
0
16
read-write
RESERVED
no description available
16
16
read-write
MODE
Features Mode Selection
0x54
32
read-write
n
0x0
0x0
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
RESERVED
no description available
8
24
read-only
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
n
0x0
0x0
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
RESERVED
no description available
8
24
read-only
OUTMASK
Output Mask
0x60
32
read-write
n
0x0
0x0
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
RESERVED
no description available
8
24
read-only
POL
Channels Polarity
0x70
32
read-write
n
0x0
0x0
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
RESERVED
no description available
8
24
read-write
PWMLOAD
FTM PWM Load
0x98
32
read-write
n
0x0
0x0
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
RESERVED
no description available
8
1
read-only
RESERVED
no description available
10
22
read-only
SC
Status And Control
0x0
32
read-write
n
0x0
0x0
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
RESERVED
no description available
8
24
read-only
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture And Compare Status
0x50
32
read-only
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
RESERVED
no description available
8
24
read-only
SWOCTRL
FTM Software Output Control
0x94
32
read-write
n
0x0
0x0
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
RESERVED
no description available
16
16
read-only
SYNC
Synchronization
0x58
32
read-write
n
0x0
0x0
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
RESERVED
no description available
8
24
read-only
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
n
0x0
0x0
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
HWINVC
no description available
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWOM
no description available
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWRSTCNT
no description available
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWSOC
no description available
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
HWWRBUF
no description available
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
RESERVED
no description available
1
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
13
3
read-only
RESERVED
no description available
21
11
read-only
SWINVC
no description available
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOM
no description available
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWRSTCNT
no description available
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWSOC
no description available
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
SWWRBUF
no description available
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
FTM2
FlexTimer Module
FTM
0x0
0x0
0x9C
registers
n
FTM2
19
INT_FTM2
19
C0SC
Channel (n) Status And Control
0x18
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C0V
Channel (n) Value
0x20
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C1SC
Channel (n) Status And Control
0x2C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C1V
Channel (n) Value
0x38
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C2SC
Channel (n) Status And Control
0x48
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C2V
Channel (n) Value
0x58
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C3SC
Channel (n) Status And Control
0x6C
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C3V
Channel (n) Value
0x80
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C4SC
Channel (n) Status And Control
0x98
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C4V
Channel (n) Value
0xB0
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
C5SC
Channel (n) Status And Control
0xCC
32
read-write
n
0x0
0x0
CHF
Channel Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CHIE
Channel Interrupt Enable
6
1
read-write
0
Disable channel interrupts. Use software polling.
#0
1
Enable channel interrupts.
#1
ELSA
Edge or Level Select
2
1
read-write
ELSB
Edge or Level Select
3
1
read-write
MSA
Channel Mode Select
4
1
read-write
MSB
Channel Mode Select
5
1
read-write
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
8
24
read-only
C5V
Channel (n) Value
0xE8
32
read-write
n
0x0
0x0
RESERVED
no description available
16
16
read-only
VAL
Channel Value
0
16
read-write
CNT
Counter
0x4
32
read-write
n
0x0
0x0
COUNT
Counter Value
0
16
read-write
RESERVED
no description available
16
16
read-only
CNTIN
Counter Initial Value
0x4C
32
read-write
n
0x0
0x0
INIT
no description available
0
16
read-write
RESERVED
no description available
16
16
read-write
COMBINE
Function For Linked Channels
0x64
32
read-write
n
0x0
0x0
COMBINE0
Combine Channels For n = 0
0
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE1
Combine Channels For n = 2
8
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE2
Combine Channels For n = 4
16
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMBINE3
Combine Channels For n = 6
24
1
read-write
0
Channels (n) and (n+1) are independent.
#0
1
Channels (n) and (n+1) are combined.
#1
COMP0
Complement Of Channel (n) For n = 0
1
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP1
Complement Of Channel (n) For n = 2
9
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP2
Complement Of Channel (n) For n = 4
17
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
COMP3
Complement Of Channel (n) for n = 6
25
1
read-write
0
The channel (n+1) output is the same as the channel (n) output.
#0
1
The channel (n+1) output is the complement of the channel (n) output.
#1
DECAP0
Dual Edge Capture Mode Captures For n = 0
3
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP1
Dual Edge Capture Mode Captures For n = 2
11
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP2
Dual Edge Capture Mode Captures For n = 4
19
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAP3
Dual Edge Capture Mode Captures For n = 6
27
1
read-write
0
The dual edge captures are inactive.
#0
1
The dual edge captures are active.
#1
DECAPEN0
Dual Edge Capture Mode Enable For n = 0
2
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
10
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
18
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DECAPEN3
Dual Edge Capture Mode Enable For n = 6
26
1
read-write
0
The Dual Edge Capture mode in this pair of channels is disabled.
#0
1
The Dual Edge Capture mode in this pair of channels is enabled.
#1
DTEN0
Deadtime Enable For n = 0
4
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN1
Deadtime Enable For n = 2
12
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN2
Deadtime Enable For n = 4
20
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
DTEN3
Deadtime Enable For n = 6
28
1
read-write
0
The deadtime insertion in this pair of channels is disabled.
#0
1
The deadtime insertion in this pair of channels is enabled.
#1
FAULTEN0
Fault Control Enable For n = 0
6
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN1
Fault Control Enable For n = 2
14
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN2
Fault Control Enable For n = 4
22
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
FAULTEN3
Fault Control Enable For n = 6
30
1
read-write
0
The fault control in this pair of channels is disabled.
#0
1
The fault control in this pair of channels is enabled.
#1
RESERVED
no description available
7
1
read-only
RESERVED
no description available
15
1
read-only
RESERVED
no description available
23
1
read-only
RESERVED
no description available
31
1
read-only
SYNCEN0
Synchronization Enable For n = 0
5
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN1
Synchronization Enable For n = 2
13
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN2
Synchronization Enable For n = 4
21
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
SYNCEN3
Synchronization Enable For n = 6
29
1
read-write
0
The PWM synchronization in this pair of channels is disabled.
#0
1
The PWM synchronization in this pair of channels is enabled.
#1
CONF
Configuration
0x84
32
read-write
n
0x0
0x0
BDMMODE
BDM Mode
6
2
read-write
GTBEEN
Global Time Base Enable
9
1
read-write
0
Use of an external global time base is disabled.
#0
1
Use of an external global time base is enabled.
#1
GTBEOUT
Global Time Base Output
10
1
read-write
0
A global time base signal generation is disabled.
#0
1
A global time base signal generation is enabled.
#1
NUMTOF
TOF Frequency
0
5
read-write
RESERVED
no description available
5
1
read-only
RESERVED
no description available
8
1
read-only
RESERVED
no description available
11
21
read-only
DEADTIME
Deadtime Insertion Control
0x68
32
read-write
n
0x0
0x0
DTPS
Deadtime Prescaler Value
6
2
read-write
0x
Divide the system clock by 1.
#0x
10
Divide the system clock by 4.
#10
11
Divide the system clock by 16.
#11
DTVAL
Deadtime Value
0
6
read-write
RESERVED
no description available
8
24
read-only
EXTTRIG
FTM External Trigger
0x6C
32
read-write
n
0x0
0x0
CH0TRIG
Channel 0 Trigger Enable
4
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH1TRIG
Channel 1 Trigger Enable
5
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH2TRIG
Channel 2 Trigger Enable
0
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH3TRIG
Channel 3 Trigger Enable
1
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH4TRIG
Channel 4 Trigger Enable
2
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
CH5TRIG
Channel 5 Trigger Enable
3
1
read-write
0
The generation of the channel trigger is disabled.
#0
1
The generation of the channel trigger is enabled.
#1
INITTRIGEN
Initialization Trigger Enable
6
1
read-write
0
The generation of initialization trigger is disabled.
#0
1
The generation of initialization trigger is enabled.
#1
RESERVED
no description available
8
24
read-write
TRIGF
Channel Trigger Flag
7
1
read-only
0
No channel trigger was generated.
#0
1
A channel trigger was generated.
#1
FILTER
Input Capture Filter Control
0x78
32
read-write
n
0x0
0x0
CH0FVAL
Channel 0 Input Filter
0
4
read-write
CH1FVAL
Channel 1 Input Filter
4
4
read-write
CH2FVAL
Channel 2 Input Filter
8
4
read-write
CH3FVAL
Channel 3 Input Filter
12
4
read-write
RESERVED
no description available
16
16
read-write
FLTCTRL
Fault Control
0x7C
32
read-write
n
0x0
0x0
FAULT0EN
Fault Input 0 Enable
0
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT1EN
Fault Input 1 Enable
1
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT2EN
Fault Input 2 Enable
2
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FAULT3EN
Fault Input 3 Enable
3
1
read-write
0
Fault input is disabled.
#0
1
Fault input is enabled.
#1
FFLTR0EN
Fault Input 0 Filter Enable
4
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR1EN
Fault Input 1 Filter Enable
5
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR2EN
Fault Input 2 Filter Enable
6
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFLTR3EN
Fault Input 3 Filter Enable
7
1
read-write
0
Fault input filter is disabled.
#0
1
Fault input filter is enabled.
#1
FFVAL
Fault Input Filter
8
4
read-write
RESERVED
no description available
12
20
read-only
FLTPOL
FTM Fault Input Polarity
0x88
32
read-write
n
0x0
0x0
FLT0POL
Fault Input 0 Polarity
0
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT1POL
Fault Input 1 Polarity
1
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT2POL
Fault Input 2 Polarity
2
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
FLT3POL
Fault Input 3 Polarity
3
1
read-write
0
The fault input polarity is active high. A one at the fault input indicates a fault.
#0
1
The fault input polarity is active low. A zero at the fault input indicates a fault.
#1
RESERVED
no description available
4
28
read-only
FMS
Fault Mode Status
0x74
32
read-write
n
0x0
0x0
FAULTF
Fault Detection Flag
7
1
read-only
0
No fault condition was detected.
#0
1
A fault condition was detected.
#1
FAULTF0
Fault Detection Flag 0
0
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF1
Fault Detection Flag 1
1
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF2
Fault Detection Flag 2
2
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTF3
Fault Detection Flag 3
3
1
read-only
0
No fault condition was detected at the fault input.
#0
1
A fault condition was detected at the fault input.
#1
FAULTIN
Fault Inputs
5
1
read-only
0
The logic OR of the enabled fault inputs is 0.
#0
1
The logic OR of the enabled fault inputs is 1.
#1
RESERVED
no description available
4
1
read-only
RESERVED
no description available
8
24
read-only
WPEN
Write Protection Enable
6
1
read-write
0
Write protection is disabled. Write protected bits can be written.
#0
1
Write protection is enabled. Write protected bits cannot be written.
#1
INVCTRL
FTM Inverting Control
0x90
32
read-write
n
0x0
0x0
INV0EN
Pair Channels 0 Inverting Enable
0
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV1EN
Pair Channels 1 Inverting Enable
1
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV2EN
Pair Channels 2 Inverting Enable
2
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
INV3EN
Pair Channels 3 Inverting Enable
3
1
read-write
0
Inverting is disabled.
#0
1
Inverting is enabled.
#1
RESERVED
no description available
4
28
read-only
MOD
Modulo
0x8
32
read-write
n
0x0
0x0
MOD
no description available
0
16
read-write
RESERVED
no description available
16
16
read-write
MODE
Features Mode Selection
0x54
32
read-write
n
0x0
0x0
CAPTEST
Capture Test Mode Enable
4
1
read-write
0
Capture test mode is disabled.
#0
1
Capture test mode is enabled.
#1
FAULTIE
Fault Interrupt Enable
7
1
read-write
0
Fault control interrupt is disabled.
#0
1
Fault control interrupt is enabled.
#1
FAULTM
Fault Control Mode
5
2
read-write
00
Fault control is disabled for all channels.
#00
01
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
#01
10
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
#10
11
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
#11
FTMEN
FTM Enable
0
1
read-write
0
Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
#0
1
All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
#1
INIT
Initialize The Channels Output
1
1
read-write
PWMSYNC
PWM Synchronization Mode
3
1
read-write
0
No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
#0
1
Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
#1
RESERVED
no description available
8
24
read-only
WPDIS
Write Protection Disable
2
1
read-write
0
Write protection is enabled.
#0
1
Write protection is disabled.
#1
OUTINIT
Initial State For Channels Output
0x5C
32
read-write
n
0x0
0x0
CH0OI
Channel 0 Output Initialization Value
0
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH1OI
Channel 1 Output Initialization Value
1
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH2OI
Channel 2 Output Initialization Value
2
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH3OI
Channel 3 Output Initialization Value
3
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH4OI
Channel 4 Output Initialization Value
4
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH5OI
Channel 5 Output Initialization Value
5
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH6OI
Channel 6 Output Initialization Value
6
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
CH7OI
Channel 7 Output Initialization Value
7
1
read-write
0
The initialization value is 0.
#0
1
The initialization value is 1.
#1
RESERVED
no description available
8
24
read-only
OUTMASK
Output Mask
0x60
32
read-write
n
0x0
0x0
CH0OM
Channel 0 Output Mask
0
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH1OM
Channel 1 Output Mask
1
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH2OM
Channel 2 Output Mask
2
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH3OM
Channel 3 Output Mask
3
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH4OM
Channel 4 Output Mask
4
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH5OM
Channel 5 Output Mask
5
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH6OM
Channel 6 Output Mask
6
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
CH7OM
Channel 7 Output Mask
7
1
read-write
0
Channel output is not masked. It continues to operate normally.
#0
1
Channel output is masked. It is forced to its inactive state.
#1
RESERVED
no description available
8
24
read-only
POL
Channels Polarity
0x70
32
read-write
n
0x0
0x0
POL0
Channel 0 Polarity
0
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL1
Channel 1 Polarity
1
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL2
Channel 2 Polarity
2
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL3
Channel 3 Polarity
3
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL4
Channel 4 Polarity
4
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL5
Channel 5 Polarity
5
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL6
Channel 6 Polarity
6
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
POL7
Channel 7 Polarity
7
1
read-write
0
The channel polarity is active high.
#0
1
The channel polarity is active low.
#1
RESERVED
no description available
8
24
read-write
PWMLOAD
FTM PWM Load
0x98
32
read-write
n
0x0
0x0
CH0SEL
Channel 0 Select
0
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH1SEL
Channel 1 Select
1
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH2SEL
Channel 2 Select
2
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH3SEL
Channel 3 Select
3
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH4SEL
Channel 4 Select
4
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH5SEL
Channel 5 Select
5
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH6SEL
Channel 6 Select
6
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
CH7SEL
Channel 7 Select
7
1
read-write
0
Do not include the channel in the matching process.
#0
1
Include the channel in the matching process.
#1
LDOK
Load Enable
9
1
read-write
0
Loading updated values is disabled.
#0
1
Loading updated values is enabled.
#1
RESERVED
no description available
8
1
read-only
RESERVED
no description available
10
22
read-only
SC
Status And Control
0x0
32
read-write
n
0x0
0x0
CLKS
Clock Source Selection
3
2
read-write
00
No clock selected. This in effect disables the FTM counter.
#00
01
System clock
#01
10
Fixed frequency clock
#10
11
External clock
#11
CPWMS
Center-Aligned PWM Select
5
1
read-write
0
FTM counter operates in Up Counting mode.
#0
1
FTM counter operates in Up-Down Counting mode.
#1
PS
Prescale Factor Selection
0
3
read-write
000
Divide by 1
#000
001
Divide by 2
#001
010
Divide by 4
#010
011
Divide by 8
#011
100
Divide by 16
#100
101
Divide by 32
#101
110
Divide by 64
#110
111
Divide by 128
#111
RESERVED
no description available
8
24
read-only
TOF
Timer Overflow Flag
7
1
read-only
0
FTM counter has not overflowed.
#0
1
FTM counter has overflowed.
#1
TOIE
Timer Overflow Interrupt Enable
6
1
read-write
0
Disable TOF interrupts. Use software polling.
#0
1
Enable TOF interrupts. An interrupt is generated when TOF equals one.
#1
STATUS
Capture And Compare Status
0x50
32
read-only
n
0x0
0x0
CH0F
Channel 0 Flag
0
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH1F
Channel 1 Flag
1
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH2F
Channel 2 Flag
2
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH3F
Channel 3 Flag
3
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH4F
Channel 4 Flag
4
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH5F
Channel 5 Flag
5
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH6F
Channel 6 Flag
6
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
CH7F
Channel 7 Flag
7
1
read-only
0
No channel event has occurred.
#0
1
A channel event has occurred.
#1
RESERVED
no description available
8
24
read-only
SWOCTRL
FTM Software Output Control
0x94
32
read-write
n
0x0
0x0
CH0OC
Channel 0 Software Output Control Enable
0
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH0OCV
Channel 0 Software Output Control Value
8
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH1OC
Channel 1 Software Output Control Enable
1
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH1OCV
Channel 1 Software Output Control Value
9
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH2OC
Channel 2 Software Output Control Enable
2
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH2OCV
Channel 2 Software Output Control Value
10
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH3OC
Channel 3 Software Output Control Enable
3
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH3OCV
Channel 3 Software Output Control Value
11
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH4OC
Channel 4 Software Output Control Enable
4
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH4OCV
Channel 4 Software Output Control Value
12
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH5OC
Channel 5 Software Output Control Enable
5
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH5OCV
Channel 5 Software Output Control Value
13
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH6OC
Channel 6 Software Output Control Enable
6
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH6OCV
Channel 6 Software Output Control Value
14
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
CH7OC
Channel 7 Software Output Control Enable
7
1
read-write
0
The channel output is not affected by software output control.
#0
1
The channel output is affected by software output control.
#1
CH7OCV
Channel 7 Software Output Control Value
15
1
read-write
0
The software output control forces 0 to the channel output.
#0
1
The software output control forces 1 to the channel output.
#1
RESERVED
no description available
16
16
read-only
SYNC
Synchronization
0x58
32
read-write
n
0x0
0x0
CNTMAX
Maximum Loading Point Enable
1
1
read-write
0
The maximum loading point is disabled.
#0
1
The maximum loading point is enabled.
#1
CNTMIN
Minimum Loading Point Enable
0
1
read-write
0
The minimum loading point is disabled.
#0
1
The minimum loading point is enabled.
#1
REINIT
FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
2
1
read-write
0
FTM counter continues to count normally.
#0
1
FTM counter is updated with its initial value when the selected trigger is detected.
#1
RESERVED
no description available
8
24
read-only
SWSYNC
PWM Synchronization Software Trigger
7
1
read-write
0
Software trigger is not selected.
#0
1
Software trigger is selected.
#1
SYNCHOM
Output Mask Synchronization
3
1
read-write
0
OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
#0
1
OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
#1
TRIG0
PWM Synchronization Hardware Trigger 0
4
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG1
PWM Synchronization Hardware Trigger 1
5
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
TRIG2
PWM Synchronization Hardware Trigger 2
6
1
read-write
0
Trigger is disabled.
#0
1
Trigger is enabled.
#1
SYNCONF
Synchronization Configuration
0x8C
32
read-write
n
0x0
0x0
CNTINC
CNTIN Register Synchronization
2
1
read-write
0
CNTIN register is updated with its buffer value at all rising edges of system clock.
#0
1
CNTIN register is updated with its buffer value by the PWM synchronization.
#1
HWINVC
no description available
19
1
read-write
0
A hardware trigger does not activate the INVCTRL register synchronization.
#0
1
A hardware trigger activates the INVCTRL register synchronization.
#1
HWOM
no description available
18
1
read-write
0
A hardware trigger does not activate the OUTMASK register synchronization.
#0
1
A hardware trigger activates the OUTMASK register synchronization.
#1
HWRSTCNT
no description available
16
1
read-write
0
A hardware trigger does not activate the FTM counter synchronization.
#0
1
A hardware trigger activates the FTM counter synchronization.
#1
HWSOC
no description available
20
1
read-write
0
A hardware trigger does not activate the SWOCTRL register synchronization.
#0
1
A hardware trigger activates the SWOCTRL register synchronization.
#1
HWTRIGMODE
Hardware Trigger Mode
0
1
read-write
0
FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#0
1
FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
#1
HWWRBUF
no description available
17
1
read-write
0
A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
#1
INVC
INVCTRL Register Synchronization
4
1
read-write
0
INVCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
INVCTRL register is updated with its buffer value by the PWM synchronization.
#1
RESERVED
no description available
1
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
13
3
read-only
RESERVED
no description available
21
11
read-only
SWINVC
no description available
11
1
read-write
0
The software trigger does not activate the INVCTRL register synchronization.
#0
1
The software trigger activates the INVCTRL register synchronization.
#1
SWOC
SWOCTRL Register Synchronization
5
1
read-write
0
SWOCTRL register is updated with its buffer value at all rising edges of system clock.
#0
1
SWOCTRL register is updated with its buffer value by the PWM synchronization.
#1
SWOM
no description available
10
1
read-write
0
The software trigger does not activate the OUTMASK register synchronization.
#0
1
The software trigger activates the OUTMASK register synchronization.
#1
SWRSTCNT
no description available
8
1
read-write
0
The software trigger does not activate the FTM counter synchronization.
#0
1
The software trigger activates the FTM counter synchronization.
#1
SWSOC
no description available
12
1
read-write
0
The software trigger does not activate the SWOCTRL register synchronization.
#0
1
The software trigger activates the SWOCTRL register synchronization.
#1
SWWRBUF
no description available
9
1
read-write
0
The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
#0
1
The software trigger activates MOD, CNTIN, and CV registers synchronization.
#1
SYNCMODE
Synchronization Mode
7
1
read-write
0
Legacy PWM synchronization is selected.
#0
1
Enhanced PWM synchronization is selected.
#1
FTMRH
Flash Memory
FTMRH
0x0
0x0
0xD
registers
n
FTMRH
5
EEPROT
EEPROM Protection Register
0x9
8
read-write
n
0x0
0x0
DPOPEN
EEPROM Protection Control
7
1
read-write
0
Enables EEPROM memory protection from program and erase with protected address range defined by DPS bits.
#0
1
Disables EEPROM memory protection from program and erase.
#1
DPS
EEPROM Protection Size
0
3
read-write
RESERVED
no description available
3
4
read-only
FCCOBHI
Flash Common Command Object Register:High
0xA
8
read-write
n
0x0
0x0
CCOB
Common Command Object Bit 15:8
0
8
read-write
FCCOBIX
Flash CCOB Index Register
0x2
8
read-write
n
0x0
0x0
CCOBIX
Common Command Register Index
0
3
read-write
RESERVED
no description available
3
5
read-only
FCCOBLO
Flash Common Command Object Register: Low
0xB
8
read-write
n
0x0
0x0
CCOB
Common Command Object Bit 7:0
0
8
read-write
FCLKDIV
Flash Clock Divider Register
0x0
8
read-write
n
0x0
0x0
FDIV
Clock Divider Bits
0
6
read-write
FDIVLCK
Clock Divider Locked
6
1
read-write
0
FDIV field is open for writing.
#0
1
FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode.
#1
FDIVLD
Clock Divider Loaded
7
1
read-only
0
FCLKDIV register has not been written since the last reset.
#0
1
FCLKDIV register has been written since the last reset.
#1
FCNFG
Flash Configuration Register
0x4
8
read-write
n
0x0
0x0
CCIE
Command Complete Interrupt Enable
7
1
read-write
0
Command complete interrupt is disabled.
#0
1
An interrupt will be requested whenever the CCIF flag in the FSTAT register is set.
#1
FDFD
Force Double Bit Fault Detect
1
1
read-write
0
Flash array read operations will set the FERSTAT[DFDIF] flag only if a double bit fault is detected.
#0
1
Any flash array read operation will force the FERSTAT[DFDIF] flag to be set and an interrupt will be generated as long as FERCNFG[DFDIE] is set.
#1
FSFD
Force Single Bit Fault Detect
0
1
read-write
0
Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected.
#0
1
Flash array read operation will force the SFDIF flag in the FERSTAT register to be set and an interrupt will be generated as long as FERCNFG[SFDIE] is set.
#1
IGNSF
Ignore Single Bit Fault
4
1
read-write
0
All single-bit faults detected during array reads are reported.
#0
1
Single-bit faults detected during array reads are not reported and the single bit fault interrupt will not be generated.
#1
RESERVED
no description available
2
2
read-only
RESERVED
no description available
5
2
read-only
FERCNFG
Flash Error Configuration Register
0x5
8
read-write
n
0x0
0x0
DFDIE
Double Bit Fault Detect Interrupt Enable
1
1
read-write
0
DFDIF interrupt is disabled.
#0
1
An interrupt will be requested whenever the DFDIF flag is set.
#1
RESERVED
no description available
2
6
read-only
SFDIE
Single Bit Fault Detect Interrupt Enable
0
1
read-write
0
SFDIF interrupt is disabled whenever the SFDIF flag is set.
#0
1
An interrupt will be requested whenever the SFDIF flag is set.
#1
FERSTAT
Flash Error Status Register
0x7
8
read-write
n
0x0
0x0
DFDIF
Double Bit Fault Detect Interrupt Flag
1
1
read-write
0
No double bit fault detected.
#0
1
Double bit fault detected or a flash array read operation returning invalid data was attempted while command running.
#1
RESERVED
no description available
2
6
read-only
SFDIF
Single Bit Fault Detect Interrupt Flag
0
1
read-write
0
No single bit fault detected.
#0
1
Single bit fault detected and corrected or a flash array read operation returning invalid data was attempted while command running.
#1
FOPT
Flash Option Register
0xC
8
read-only
n
0x0
0x0
NV
Nonvolatile Bits
0
8
read-only
FPROT
Flash Protection Register
0x8
8
read-write
n
0x0
0x0
FPHDIS
Flash Protection Higher Address Range Disable
5
1
read-write
0
Protection/Unprotection enabled.
#0
1
Protection/Unprotection disabled.
#1
FPHS
Flash Protection Higher Address Size
3
2
read-write
FPLDIS
Flash Protection Lower Address Range Disable
2
1
read-write
0
Protection/Unprotection enabled.
#0
1
Protection/Unprotection disabled.
#1
FPLS
Flash Protection Lower Address Size
0
2
read-write
FPOPEN
Flash Protection Operation Enable
7
1
read-write
0
When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits.
#0
1
When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits.
#1
RESERVED
no description available
6
1
read-only
RNV6
Reserved Nonvolatile Bit
6
1
read-only
FSEC
Flash Security Register
0x1
8
read-only
n
0x0
0x0
KEYEN
Backdoor Key Security Enable Bits
6
2
read-only
00
Disabled
#00
01
Disabled
#01
10
Enabled
#10
11
Disabled
#11
RESERVED
no description available
2
4
read-only
SEC
Flash Security Bits
0
2
read-only
00
Secured
#00
01
Secured
#01
10
Unsecured
#10
11
Secured
#11
FSTAT
Flash Status Register
0x6
8
read-write
n
0x0
0x0
ACCERR
Flash Access Error Flag
5
1
read-write
0
No access error is detected.
#0
1
Access error is detected.
#1
CCIF
Command Complete Interrupt Flag
7
1
read-write
0
Flash command is in progress.
#0
1
Flash command has completed.
#1
FPVIOL
Flash Protection Violation Flag
4
1
read-write
0
No protection violation is detected.
#0
1
Protection violation is detected.
#1
MGBUSY
Memory Controller Busy Flag
3
1
read-only
0
Memory controller is idle.
#0
1
Memory controller is busy executing a flash command (CCIF = 0).
#1
MGSTAT
Memory Controller Command Completion Status Flag
0
2
read-only
RESERVED
no description available
2
1
read-only
RESERVED
no description available
6
1
read-only
FTMRH_FlashConfig
Flash configuration field
FTMRH_FlashConfig
0x0
0x0
0x10
registers
n
BACKKEY0
Backdoor Comparison Key 0
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY1
Backdoor Comparison Key 1
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY2
Backdoor Comparison Key 2
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY3
Backdoor Comparison Key 3
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY4
Backdoor Comparison Key 4
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY5
Backdoor Comparison Key 5
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY6
Backdoor Comparison Key 6
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY7
Backdoor Comparison Key 7
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
EEPROT
Non-volatile D-Flash Protection Register
0xC
8
read-only
n
0x0
0x0
DPOPEN
no description available
7
1
read-only
DPS
no description available
0
3
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
FOPT
Non-volatile Flash Option Register
0xF
8
read-only
n
0x0
0x0
RESERVED
no description available
6
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
2
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
7
1
read-only
FPROT
Non-volatile P-Flash Protection Register
0xD
8
read-only
n
0x0
0x0
FPHDIS
no description available
5
1
read-only
FPHS
no description available
3
2
read-only
FPLDIS
no description available
2
1
read-only
FPLS
no description available
0
2
read-only
FPOPEN
no description available
7
1
read-only
RESERVED
no description available
6
1
read-only
FSEC
Non-volatile Flash Security Register
0xE
8
read-only
n
0x0
0x0
KEYEN
Backdoor Key Security Enable
6
2
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
SEC
Flash Security
0
2
read-only
NV_BACKKEY0
Backdoor Comparison Key 0
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY1
Backdoor Comparison Key 1
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY2
Backdoor Comparison Key 2
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY3
Backdoor Comparison Key 3
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY4
Backdoor Comparison Key 4
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY5
Backdoor Comparison Key 5
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY6
Backdoor Comparison Key 6
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY7
Backdoor Comparison Key 7
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_EEPROT
Non-volatile D-Flash Protection Register
0xC
8
read-only
n
0x0
0x0
DPOPEN
no description available
7
1
read-only
00
Enables EEPROM memory protection
#00
01
Disables EEPROM memory protection
#01
DPS
no description available
0
3
read-only
000
Flash address range: 0x00_0000 - 0x00_001F; protected size: 32 bytes
#000
001
Flash address range: 0x00_0000 - 0x00_003F; protected size: 64 bytes
#001
010
Flash address range: 0x00_0000 - 0x00_005F; protected size: 96 bytes
#010
011
Flash address range: 0x00_0000 - 0x00_007F; protected size: 128 bytes
#011
100
Flash address range: 0x00_0000 - 0x00_009F; protected size: 160 bytes
#100
101
Flash address range: 0x00_0000 - 0x00_00BF; protected size: 192 bytes
#101
110
Flash address range: 0x00_0000 - 0x00_00DF; protected size: 224 bytes
#110
111
Flash address range: 0x00_0000 - 0x00_00FF; protected size: 256 bytes
#111
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
NV_FOPT
Non-volatile Flash Option Register
0xF
8
read-only
n
0x0
0x0
RESERVED
no description available
0
1
read-only
RESERVED
no description available
1
1
read-only
RESERVED
no description available
2
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
RESERVED
no description available
7
1
read-only
NV_FPROT
Non-volatile P-Flash Protection Register
0xD
8
read-only
n
0x0
0x0
FPHDIS
no description available
5
1
read-only
00
Protection/Unprotection enabled
#00
01
Protection/Unprotection disabled
#01
FPHS
no description available
3
2
read-only
00
Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB
#00
01
Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB
#01
10
Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB
#10
11
Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB
#11
FPLDIS
no description available
2
1
read-only
00
Protection/Unprotection enabled
#00
01
Protection/Unprotection disabled
#01
FPLS
no description available
0
2
read-only
00
Address range: 0x00_0000-0x00_07FF; protected size: 2 KB
#00
01
Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB
#01
10
Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB
#10
11
Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB
#11
FPOPEN
no description available
7
1
read-only
00
FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1
#00
01
FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits
#01
RESERVED
no description available
6
1
read-only
NV_FSEC
Non-volatile Flash Security Register
0xE
8
read-only
n
0x0
0x0
KEYEN
Backdoor Key Security Enable
6
2
read-only
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
RESERVED
no description available
2
1
read-only
RESERVED
no description available
3
1
read-only
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
SEC
Flash Security
0
2
read-only
10
MCU security status is unsecure
#10
11
MCU security status is secure
#11
GPIOA
General Purpose Input/Output
GPIO
0x0
0x0
0x1C
registers
n
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
GPIOB
General Purpose Input/Output
GPIO
0x0
0x0
0x1C
registers
n
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
I2C0
Inter-Integrated Circuit
I2C0
0x0
0x0
0xC
registers
n
I2C0
8
INT_I2C0
8
A1
I2C Address Register 1
0x0
8
read-write
n
0x0
0x0
AD
Address
1
7
read-write
RESERVED
no description available
0
1
read-only
A2
I2C Address Register 2
0x9
8
read-write
n
0x0
0x0
RESERVED
no description available
0
1
read-only
SAD
SMBus Address
1
7
read-write
C1
I2C Control Register 1
0x2
8
read-write
n
0x0
0x0
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
RESERVED
no description available
0
1
read-only
RSTA
Repeat START
2
1
write-only
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
C2
I2C Control Register 2
0x5
8
read-write
n
0x0
0x0
AD
Slave Address
0
3
read-write
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
RESERVED
no description available
4
1
read-only
RESERVED
no description available
5
1
read-only
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
D
I2C Data I/O register
0x4
8
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
F
I2C Frequency Divider register
0x1
8
read-write
n
0x0
0x0
ICR
ClockRate
0
6
read-write
MULT
no description available
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
11
Reserved
#11
FLT
I2C Programmable Input Glitch Filter register
0x6
8
read-write
n
0x0
0x0
FLT
I2C Programmable Filter Factor
0
5
read-write
0
No filter/bypass
#0
RESERVED
no description available
5
2
read-only
RESERVED
no description available
7
1
read-write
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
RA
I2C Range Address register
0x7
8
read-write
n
0x0
0x0
RAD
Range Slave Address
1
7
read-write
RESERVED
no description available
0
1
read-only
S
I2C Status register
0x3
8
read-write
n
0x0
0x0
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
n
0x0
0x0
SSLT
no description available
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
n
0x0
0x0
SSLT
no description available
0
8
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
n
0x0
0x0
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the bus clock / 64
#0
1
Timeout counter counts at the frequency of the bus clock
#1
ICS
Clock management
ICS
0x0
0x0
0x5
registers
n
ICS
27
C1
ICS Control Register 1
0x0
8
read-write
n
0x0
0x0
CLKS
Clock Source Select
6
2
read-write
00
Output of FLL is selected.
#00
01
Internal reference clock is selected.
#01
10
External reference clock is selected.
#10
11
Reserved, defaults to 00.
#11
IRCLKEN
Internal Reference Clock Enable
1
1
read-write
0
ICSIRCLK is inactive.
#0
1
ICSIRCLK is active.
#1
IREFS
Internal Reference Select
2
1
read-write
0
External reference clock is selected.
#0
1
Internal reference clock is selected.
#1
IREFSTEN
Internal Reference Stop Enable
0
1
read-write
0
Internal reference clock is disabled in Stop mode.
#0
1
Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop.
#1
RDIV
Reference Divider
3
3
read-write
C2
ICS Control Register 2
0x1
8
read-write
n
0x0
0x0
BDIV
Bus Frequency Divider
5
3
read-write
000
Encoding 0-Divides the selected clock by 1.
#000
001
Encoding 1-Divides the selected clock by 2 (reset default).
#001
010
Encoding 2-Divides the selected clock by 4.
#010
011
Encoding 3-Divides the selected clock by 8.
#011
100
Encoding 4-Divides the selected clock by 16.
#100
101
Encoding 5-Divides the selected clock by 32.
#101
110
Encoding 6-Divides the selected clock by 64.
#110
111
Encoding 7-Divides the selected clock by 128.
#111
LP
Low Power Select
4
1
read-write
0
FLL is not disabled in bypass mode.
#0
1
FLL is disabled in bypass modes unless BDM is active.
#1
RESERVED
no description available
0
4
read-only
C3
ICS Control Register 3
0x2
8
read-write
n
0x0
0x0
SCTRIM
Slow Internal Reference Clock Trim Setting
0
8
read-write
C4
ICS Control Register 4
0x3
8
read-write
n
0x0
0x0
CME
Clock Monitor Enable
5
1
read-write
0
Clock monitor is disabled.
#0
1
Generates a reset request on loss of external clock.
#1
LOLIE
Loss of Lock Interrupt
7
1
read-write
0
No request on loss of lock.
#0
1
Generates an interrupt request on loss of lock.
#1
RESERVED
no description available
1
4
read-only
RESERVED
no description available
6
1
read-only
SCFTRIM
Slow Internal Reference Clock Fine Trim
0
1
read-write
S
ICS Status Register
0x4
8
read-only
n
0x0
0x0
CLKST
Clock Mode Status
2
2
read-only
00
Output of FLL is selected.
#00
01
FLL Bypassed, internal reference clock is selected.
#01
10
FLL Bypassed, external reference clock is selected.
#10
11
Reserved.
#11
IREFST
Internal Reference Status
4
1
read-only
0
Source of reference clock is external clock.
#0
1
Source of reference clock is internal clock.
#1
LOCK
Lock Status
6
1
read-only
0
FLL is currently unlocked.
#0
1
FLL is currently locked.
#1
LOLS
Loss of Lock Status
7
1
read-only
0
FLL has not lost lock since LOLS was last cleared.
#0
1
FLL has lost lock since LOLS was last cleared.
#1
RESERVED
no description available
0
2
read-only
RESERVED
no description available
5
1
read-only
IRQ
Interrupt
IRQ
0x0
0x0
0x1
registers
n
IRQ
7
SC
Interrupt Pin Request Status and Control Register
0x0
8
read-write
n
0x0
0x0
IRQACK
IRQ Acknowledge
2
1
write-only
IRQEDG
Interrupt Request (IRQ) Edge Select
5
1
read-write
0
IRQ is falling-edge or falling-edge/low-level sensitive.
#0
1
IRQ is rising-edge or rising-edge/high-level sensitive.
#1
IRQF
IRQ Flag
3
1
read-only
0
No IRQ request
#0
1
IRQ event is detected.
#1
IRQIE
IRQ Interrupt Enable
1
1
read-write
0
Interrupt request when IRQF set is disabled (use polling).
#0
1
Interrupt requested whenever IRQF = 1.
#1
IRQMOD
IRQ Detection Mode
0
1
read-write
0
IRQ event is detected only on falling/rising edges.
#0
1
IRQ event is detected on falling/rising edges and low/high levels.
#1
IRQPDD
Interrupt Request (IRQ) Pull Device Disable
6
1
read-write
0
IRQ pull device enabled if IRQPE = 1.
#0
1
IRQ pull device disabled if IRQPE = 1.
#1
IRQPE
IRQ Pin Enable
4
1
read-write
0
IRQ pin function is disabled.
#0
1
IRQ pin function is enabled.
#1
RESERVED
no description available
7
1
read-only
KBI0
Keyboard interrupts
KBI
0x0
0x0
0x3
registers
n
KBI0
24
INT_KBI0
24
ES
KBIx Edge Select Register
0x2
8
read-write
n
0x0
0x0
KBEDG
KBI Edge Selects
0
8
read-write
0
Falling edge/low level.
#0
1
Rising edge/high level.
#1
PE
KBIx Pin Enable Register
0x1
8
read-write
n
0x0
0x0
KBIPE
KBI Pin Enables
0
8
read-write
0
Pin is not enabled as KBI interrupt.
#0
1
Pin is enabled as KBI interrupt.
#1
SC
KBI Status and Control Register
0x0
8
read-write
n
0x0
0x0
KBACK
KBI Acknowledge
2
1
write-only
KBF
KBI Interrupt Flag
3
1
read-only
0
KBI interrupt request not detected.
#0
1
KBI interrupt request detected.
#1
KBIE
KBI Interrupt Enable
1
1
read-write
0
KBI interrupt not enabled.
#0
1
KBI interrupt enabled.
#1
KBMOD
KBI Detection Mode
0
1
read-write
0
Keyboard detects edges only.
#0
1
Keyboard detects both edges and levels.
#1
RESERVED
no description available
4
4
read-only
KBI1
Keyboard interrupts
KBI
0x0
0x0
0x3
registers
n
KBI1
25
INT_KBI1
25
ES
KBIx Edge Select Register
0x2
8
read-write
n
0x0
0x0
KBEDG
KBI Edge Selects
0
8
read-write
0
Falling edge/low level.
#0
1
Rising edge/high level.
#1
PE
KBIx Pin Enable Register
0x1
8
read-write
n
0x0
0x0
KBIPE
KBI Pin Enables
0
8
read-write
0
Pin is not enabled as KBI interrupt.
#0
1
Pin is enabled as KBI interrupt.
#1
SC
KBI Status and Control Register
0x0
8
read-write
n
0x0
0x0
KBACK
KBI Acknowledge
2
1
write-only
KBF
KBI Interrupt Flag
3
1
read-only
0
KBI interrupt request not detected.
#0
1
KBI interrupt request detected.
#1
KBIE
KBI Interrupt Enable
1
1
read-write
0
KBI interrupt not enabled.
#0
1
KBI interrupt enabled.
#1
KBMOD
KBI Detection Mode
0
1
read-write
0
Keyboard detects edges only.
#0
1
Keyboard detects both edges and levels.
#1
RESERVED
no description available
4
4
read-only
MCM
Core Platform Miscellaneous Control Module
MCM
0x0
0x8
0x8
registers
n
PLACR
Platform Control Register
0xC
32
read-write
n
0x0
0x0
CFCC
Clear Flash Controller Cache
10
1
write-only
DFCC
Disable Flash Controller Cache
13
1
read-write
0
Enable flash controller cache.
#0
1
Disable flash controller cache.
#1
DFCDA
Disable Flash Controller Data Caching
11
1
read-write
0
Enable flash controller data caching
#0
1
Disable flash controller data caching.
#1
DFCIC
Disable Flash Controller Instruction Caching
12
1
read-write
0
Enable flash controller instruction caching.
#0
1
Disable flash controller instruction caching.
#1
DFCS
Disable Flash Controller Speculation
15
1
read-write
0
Enable flash controller speculation.
#0
1
Disable flash controller speculation.
#1
EFDS
Enable Flash Data Speculation
14
1
read-write
0
Disable flash data speculation.
#0
1
Enable flash data speculation.
#1
ESFC
Enable Stalling Flash Controller
16
1
read-write
0
Disable stalling flash controller when flash is busy.
#0
1
Enable stalling flash controller when flash is busy.
#1
RESERVED
no description available
0
10
read-only
RESERVED
no description available
17
15
read-only
PLAMC
Crossbar Switch (AXBS) Master Configuration
0xA
16
read-only
n
0x0
0x0
AMC
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0
8
read-only
0
A bus master connection to AXBS input port n is absent
#0
1
A bus master connection to AXBS input port n is present
#1
RESERVED
no description available
8
8
read-only
PLASC
Crossbar Switch (AXBS) Slave Configuration
0x8
16
read-only
n
0x0
0x0
ASC
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
0
8
read-only
0
A bus slave connection to AXBS input port n is absent
#0
1
A bus slave connection to AXBS input port n is present
#1
RESERVED
no description available
8
8
read-only
NVIC
Nested Vectored Interrupt Controller
NVIC
0x0
0x0
0x320
registers
n
ICER
Interrupt Clear Enable Register
0x80
32
read-write
n
0x0
0x0
CLRENA
Interrupt clear-enable bits
0
32
read-write
ICPR
Interrupt Clear Pending Register
0x180
32
read-write
n
0x0
0x0
CLRPEND
Interrupt clear-pending bits
0
32
read-write
IPR0
Interrupt Priority Register n
0x300
32
read-write
n
0x0
0x0
PRI_0
Priority of interrupt 0
0
8
read-write
PRI_1
Priority of interrupt 1
8
8
read-write
PRI_2
Priority of interrupt 2
16
8
read-write
PRI_3
Priority of interrupt 3
24
8
read-write
IPR1
Interrupt Priority Register n
0x304
32
read-write
n
0x0
0x0
PRI_4
Priority of interrupt 4
0
8
read-write
PRI_5
Priority of interrupt 5
8
8
read-write
PRI_6
Priority of interrupt 6
16
8
read-write
PRI_7
Priority of interrupt 7
24
8
read-write
IPR2
Interrupt Priority Register n
0x308
32
read-write
n
0x0
0x0
PRI_10
Priority of interrupt 10
16
8
read-write
PRI_11
Priority of interrupt 11
24
8
read-write
PRI_8
Priority of interrupt 8
0
8
read-write
PRI_9
Priority of interrupt 9
8
8
read-write
IPR3
Interrupt Priority Register n
0x30C
32
read-write
n
0x0
0x0
PRI_12
Priority of interrupt 11
0
8
read-write
PRI_13
Priority of interrupt 12
8
8
read-write
PRI_14
Priority of interrupt 14
16
8
read-write
PRI_15
Priority of interrupt 15
24
8
read-write
IPR4
Interrupt Priority Register n
0x310
32
read-write
n
0x0
0x0
PRI_16
Priority of interrupt 17
0
8
read-write
PRI_17
Priority of interrupt 18
8
8
read-write
PRI_18
Priority of interrupt 19
16
8
read-write
PRI_19
Priority of interrupt 20
24
8
read-write
IPR5
Interrupt Priority Register n
0x314
32
read-write
n
0x0
0x0
PRI_20
Priority of interrupt 0
0
8
read-write
PRI_21
Priority of interrupt 21
8
8
read-write
PRI_22
Priority of interrupt 22
16
8
read-write
PRI_23
Priority of interrupt 23
24
8
read-write
IPR6
Interrupt Priority Register n
0x318
32
read-write
n
0x0
0x0
PRI_24
Priority of interrupt 24
0
8
read-write
PRI_25
Priority of interrupt 25
8
8
read-write
PRI_26
Priority of interrupt 26
16
8
read-write
PRI_27
Priority of interrupt 27
24
8
read-write
IPR7
Interrupt Priority Register n
0x31C
32
read-write
n
0x0
0x0
PRI_28
Priority of interrupt 28
0
8
read-write
PRI_29
Priority of interrupt 29
8
8
read-write
PRI_30
Priority of interrupt 30
16
8
read-write
PRI_31
Priority of interrupt 31
24
8
read-write
ISER
Interrupt Set Enable Register
0x0
32
read-write
n
0x0
0x0
SETENA
Interrupt set enable bits
0
32
read-write
ISPR
Interrupt Set Pending Register
0x100
32
read-write
n
0x0
0x0
SETPEND
Interrupt set-pending bits
0
32
read-write
OSC
Oscillator
OSC
0x0
0x0
0x1
registers
n
CR
OSC Control Register
0x0
8
read-write
n
0x0
0x0
HGO
High Gain Oscillator Select
1
1
read-write
0
Low-power mode
#0
1
High-gain mode
#1
OSCEN
OSC Enable
7
1
read-write
0
OSC module is disabled.
#0
1
OSC module is enabled.
#1
OSCINIT
OSC Initialization
0
1
read-only
0
Oscillator initialization is not complete.
#0
1
Oscillator initialization is completed.
#1
OSCOS
OSC Output Select
4
1
read-write
0
External clock source from EXTAL pin is selected.
#0
1
Oscillator clock source is selected.
#1
OSCSTEN
OSC Enable in Stop mode
5
1
read-write
0
OSC clock is disabled in Stop mode.
#0
1
OSC clock stays enabled in Stop mode.
#1
RANGE
Frequency Range Select
2
1
read-write
0
Low frequency range of 32 kHz.
#0
1
High frequency range of 4-20 MHz.
#1
RESERVED
no description available
3
1
read-only
RESERVED
no description available
6
1
read-only
PIT
Periodic Interrupt Timer
PIT
0x0
0x0
0x120
registers
n
PIT_CH0
22
INT_PIT_CH0
22
PIT_CH1
23
INT_PIT_CH1
23
CVAL0
Current Timer Value Register
0x208
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
CVAL1
Current Timer Value Register
0x31C
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
LDVAL0
Timer Load Value Register
0x200
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LDVAL1
Timer Load Value Register
0x310
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
MCR
PIT Module Control Register
0x0
32
read-write
n
0x0
0x0
FRZ
Freeze
0
1
read-write
0
Timers continue to run in Debug mode.
#0
1
Timers are stopped in Debug mode.
#1
MDIS
Module Disable - (PIT section)
1
1
read-write
0
Clock for standard PIT timers is enabled.
#0
1
Clock for standard PIT timers is disabled.
#1
RESERVED
no description available
2
1
read-only
RESERVED
no description available
3
29
read-only
TCTRL0
Timer Control Register
0x210
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
RESERVED
no description available
3
29
read-only
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TCTRL1
Timer Control Register
0x328
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
RESERVED
no description available
3
29
read-only
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TFLG0
Timer Flag Register
0x218
32
read-write
n
0x0
0x0
RESERVED
no description available
1
31
read-only
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
TFLG1
Timer Flag Register
0x334
32
read-write
n
0x0
0x0
RESERVED
no description available
1
31
read-only
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
PMC
Power management
PMC
0x0
0x0
0x2
registers
n
LVD_LVW
6
INT_LVD_LVW
6
SPMSC1
System Power Management Status and Control 1 Register
0x0
8
read-write
n
0x0
0x0
BGBDS
Bandgap Buffer Drive Select
1
1
read-write
0
Bandgap buffer is enabled in low-drive mode if BGBE = 1.
#0
1
Bandgap buffer is enabled in high-drive mode if BGBE = 1.
#1
BGBE
Bandgap Buffer Enable
0
1
read-write
0
Bandgap buffer is disabled.
#0
1
Bandgap buffer is enabled.
#1
LVDE
Low-Voltage Detect Enable
2
1
read-write
0
LVD logic is disabled.
#0
1
LVD logic is enabled.
#1
LVDRE
Low-Voltage Detect Reset Enable
4
1
read-write
0
LVD events do not generate hardware resets.
#0
1
Forces an MCU reset when an enabled low-voltage detect event occurs.
#1
LVDSE
Low-Voltage Detect Stop Enable
3
1
read-write
0
Low-voltage detect is disabled during Stop mode.
#0
1
Low-voltage detect is enabled during Stop mode.
#1
LVWACK
Low-Voltage Warning Acknowledge
6
1
write-only
LVWF
Low-Voltage Warning Flag
7
1
read-only
0
Low-voltage warning is not present.
#0
1
Low-voltage warning is present or was present.
#1
LVWIE
Low-Voltage Warning Interrupt Enable
5
1
read-write
0
Hardware interrupt is disabled (use polling).
#0
1
Requests a hardware interrupt when LVWF = 1.
#1
SPMSC2
System Power Management Status and Control 2 Register
0x1
8
read-write
n
0x0
0x0
LVDV
Low-Voltage Detect Voltage Select
6
1
read-write
0
Low trip point is selected (VLVD = VLVDL).
#0
1
High trip point is selected (VLVD = VLVDH).
#1
LVWV
Low-Voltage Warning Voltage Select
4
2
read-write
00
Low trip point is selected (VLVW = VLVW1).
#00
01
Middle 1 trip point is selected (VLVW = VLVW2).
#01
10
Middle 2 trip point is selected (VLVW = VLVW3).
#10
11
High trip point is selected (VLVW = VLVW4).
#11
RESERVED
no description available
0
4
read-only
RESERVED
no description available
7
1
read-only
PORT
Port control and interrupts
PORT
0x0
0x0
0x10
registers
n
HDRVE
Port High Drive Enable Register
0xC
32
read-write
n
0x0
0x0
PTB4
High Current Drive Capability of PTB4
0
1
read-write
0
PTB4 is disabled to offer high current drive capability.
#0
1
PTB4 is enabled to offer high current drive capability.
#1
PTB5
High Current Drive Capability of PTB5
1
1
read-write
0
PTB5 is disabled to offer high current drive capability.
#0
1
PTB5 is enabled to offer high current drive capability.
#1
PTD0
High Current Drive Capability of PTD0
2
1
read-write
0
PTD0 is disabled to offer high current drive capability.
#0
1
PTD0 is enabled to offer high current drive capability.
#1
PTD1
High Current Drive Capability of PTD1
3
1
read-write
0
PTD1 is disabled to offer high current drive capability.
#0
1
PTD1 is enable to offer high current drive capability.
#1
PTE0
High Current Drive Capability of PTE0
4
1
read-write
0
PTE0 is disabled to offer high current drive capability.
#0
1
PTE0 is enable to offer high current drive capability.
#1
PTE1
High Current Drive Capability of PTE1
5
1
read-write
0
PTE1 is disabled to offer high current drive capability.
#0
1
PTE1 is enabled to offer high current drive capability.
#1
PTH0
High Current Drive Capability of PTH0
6
1
read-write
0
PTH0 is disabled to offer high current drive capability.
#0
1
PTH0 is enabled to offer high current drive capability.
#1
PTH1
High Current Drive Capability of PTH1
7
1
read-write
0
PTH1 is disabled to offer high current drive capability.
#0
1
PTH1 is enabled to offer high current drive capability.
#1
RESERVED
no description available
8
24
read-only
IOFLT
Port Filter Register
0x0
32
read-write
n
0x0
0x0
FLTA
Filter Selection for Input from PTA
0
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTB
Filter Selection for Input from PTB
2
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTC
Filter Selection for Input from PTC
4
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTD
Filter Selection for Input from PTD
6
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTDIV1
Filter Division Set 1
24
2
read-write
00
BUSCLK/2
#00
01
BUSCLK/4
#01
10
BUSCLK/8
#10
11
BUSCLK/16
#11
FLTDIV2
Filter Division Set 2
26
3
read-write
000
BUSCLK/32
#000
001
BUSCLK/64
#001
010
BUSCLK/128
#010
011
BUSCLK/256
#011
100
BUSCLK/512
#100
101
BUSCLK/1024
#101
110
BUSCLK/2048
#110
111
BUSCLK/4096
#111
FLTDIV3
Filter Division Set 3
29
3
read-write
000
LPOCLK
#000
001
LPOCLK/2
#001
010
LPOCLK/4
#010
011
LPOCLK/8
#011
100
LPOCLK/16
#100
101
LPOCLK/32
#101
110
LPOCLK/64
#110
111
LPOCLK/128
#111
FLTE
Filter Selection for Input from PTD
8
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTF
Filter Selection for Input from PTF
10
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTG
Filter Selection for Input from PTG
12
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTH
Filter Selection for Input from PTH
14
2
read-write
00
BUSCLK
#00
01
FLTDIV1
#01
10
FLTDIV2
#10
11
FLTDIV3
#11
FLTKBI0
Filter selection for Input from KBI0
18
2
read-write
00
No filter.
#00
01
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
#01
10
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
#10
11
FLTDIV3
#11
FLTKBI1
Filter Selection for Input from KBI1
20
2
read-write
00
No filter
#00
01
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
#01
10
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
#10
11
FLTDIV3
#11
FLTNMI
Filter Selection for Input from NMI_b
22
2
read-write
00
No filter.
#00
01
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
#01
10
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
#10
11
FLTDIV3
#11
FLTRST
Filter Selection for Input from RESET/IRQ
16
2
read-write
00
No filter.
#00
01
Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically.
#01
10
Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically.
#10
11
FLTDIV3
#11
PUEH
Port Pullup Enable High Register
0x8
32
read-write
n
0x0
0x0
PTEPE0
Pull Enable for Port E Bit 0
0
1
read-write
0
Pullup is disabled for port E bit 0.
#0
1
Pullup is enabled for port E bit 0.
#1
PTEPE1
Pull Enable for Port E Bit 1
1
1
read-write
0
Pullup is disabled for port E bit 1.
#0
1
Pullup is enabled for port E bit 1.
#1
PTEPE2
Pull Enable for Port E Bit 2
2
1
read-write
0
Pullup is disabled for port E bit 2.
#0
1
Pullup is enabled for port E bit 2.
#1
PTEPE3
Pull Enable for Port E Bit 3
3
1
read-write
0
Pullup is disabled for port E bit 3.
#0
1
Pullup is enabled for port E bit 3.
#1
PTEPE4
Pull Enable for Port E Bit 4
4
1
read-write
0
Pullup is disabled for port E bit 4.
#0
1
Pullup is enabled for port E bit 4.
#1
PTEPE5
Pull Enable for Port E Bit 5
5
1
read-write
0
Pullup is disabled for port E bit 5.
#0
1
Pullup is enabled for port E bit 5.
#1
PTEPE6
Pull Enable for Port E Bit 6
6
1
read-write
0
Pullup is disabled for port E bit 6.
#0
1
Pullup is enabled for port E bit 6.
#1
PTEPE7
Pull Enable for Port E Bit 7
7
1
read-write
0
Pullup is disabled for port E bit 7.
#0
1
Pullup is enabled for port E bit 7.
#1
PTFPE0
Pull Enable for Port F Bit 0
8
1
read-write
0
Pullup is disabled for port F bit 0.
#0
1
Pullup is enabled for port F bit 0.
#1
PTFPE1
Pull Enable for Port F Bit 1
9
1
read-write
0
Pullup is disabled for port F bit 1.
#0
1
Pullup is enabled for port F bit 1.
#1
PTFPE2
Pull Enable for Port F Bit 2
10
1
read-write
0
Pullup is disabled for port F bit 2.
#0
1
Pullup is enabled for port F bit 2.
#1
PTFPE3
Pull Enable for Port F Bit 3
11
1
read-write
0
Pullup is disabled for port F bit 3.
#0
1
Pullup is enabled for port F bit 3.
#1
PTFPE4
Pull Enable for Port F Bit 4
12
1
read-write
0
Pullup is disabled for port F bit 4.
#0
1
Pullup is enabled for port F bit 4.
#1
PTFPE5
Pull Enable for Port F Bit 5
13
1
read-write
0
Pullup is disabled for port F bit 5.
#0
1
Pullup is enabled for port F bit 5.
#1
PTFPE6
Pull Enable for Port F Bit 6
14
1
read-write
0
Pullup is disabled for port F bit 6.
#0
1
Pullup is enabled for port F bit 6.
#1
PTFPE7
Pull Enable for Port F Bit 7
15
1
read-write
0
Pullup is disabled for port F bit 7.
#0
1
Pullup is enabled for port F bit 7.
#1
PTGPE0
Pull Enable for Port G Bit 0
16
1
read-write
0
Pullup is disabled for port G bit 0.
#0
1
Pullup is enabled for port G bit 0.
#1
PTGPE1
Pull Enable for Port G Bit 1
17
1
read-write
0
Pullup is disabled for port G bit 1.
#0
1
Pullup is enabled for port G bit 1.
#1
PTGPE2
Pull Enable for Port G Bit 2
18
1
read-write
0
Pullup is disabled for port G bit 2.
#0
1
Pullup is enabled for port G bit 2.
#1
PTGPE3
Pull Enable for Port G Bit 3
19
1
read-write
0
Pullup is disabled for port G bit 3.
#0
1
Pullup is enabled for port G bit 3.
#1
PTHPE0
Pull Enable for Port H Bit 0
24
1
read-write
0
Pullup is disabled for port H bit 0.
#0
1
Pullup is enabled for port H bit 0.
#1
PTHPE1
Pull Enable for Port H Bit 1
25
1
read-write
0
Pullup is disabled for port H bit 1.
#0
1
Pullup is enabled for port H bit 1.
#1
PTHPE2
Pull Enable for Port H Bit 2
26
1
read-write
0
Pullup is disabled for port H bit 2.
#0
1
Pullup is enabled for port H bit 2.
#1
PTHPE6
Pull Enable for Port H Bit 6
30
1
read-write
0
Pullup is disabled for port H bit 6.
#0
1
Pullup is enabled for port H bit 6.
#1
PTHPE7
Pull Enable for Port H Bit 7
31
1
read-write
0
Pullup is disabled for port H bit 7.
#0
1
Pullup is enabled for port H bit 7.
#1
RESERVED
no description available
20
4
read-only
RESERVED
no description available
27
3
read-only
PUEL
Port Pullup Enable Low Register
0x4
32
read-write
n
0x0
0x0
PTAPE0
Pull Enable for Port A Bit 0
0
1
read-write
0
Pullup is disabled for port A bit 0.
#0
1
Pullup is enabled for port A bit 0.
#1
PTAPE1
Pull Enable for Port A Bit 1
1
1
read-write
0
Pullup is disabled for port A bit 1.
#0
1
Pullup is enabled for port A bit 1.
#1
PTAPE2
Pull Enable for Port A Bit 2
2
1
read-write
0
Pullup is disabled for port A bit 2.
#0
1
Pullup is enabled for port A bit 2.
#1
PTAPE3
Pull Enable for Port A Bit 3
3
1
read-write
0
Pullup is disabled for port A bit 3.
#0
1
Pullup is enabled for port A bit 3.
#1
PTAPE4
Pull Enable for Port A Bit 4
4
1
read-write
0
Pullup is disabled for port A bit 4.
#0
1
Pullup is enabled for port A bit 4.
#1
PTAPE5
Pull Enable for Port A Bit 5
5
1
read-write
0
Pullup is disabled for port A bit 5.
#0
1
Pullup is enabled for port A bit 5.
#1
PTAPE6
Pull Enable for Port A Bit 6
6
1
read-write
0
Pullup is disabled for port A bit 6.
#0
1
Pullup is enabled for port A bit 6.
#1
PTAPE7
Pull Enable for Port A Bit 7
7
1
read-write
0
Pullup is disabled for port A bit 7.
#0
1
Pullup is enabled for port A bit 7.
#1
PTBPE0
Pull Enable for Port B Bit 0
8
1
read-write
0
Pullup is disabled for port B bit 0.
#0
1
Pullup is enabled for port B bit 0.
#1
PTBPE1
Pull Enable for Port B Bit 1
9
1
read-write
0
Pullup is disabled for port B bit 1.
#0
1
Pullup is enabled for port B bit 1.
#1
PTBPE2
Pull Enable for Port B Bit 2
10
1
read-write
0
Pullup is disabled for port B bit 2.
#0
1
Pullup is enabled for port B bit 2.
#1
PTBPE3
Pull Enable for Port B Bit 3
11
1
read-write
0
Pullup is disabled for port B bit 3.
#0
1
Pullup is enabled for port B bit 3.
#1
PTBPE4
Pull Enable for Port B Bit 4
12
1
read-write
0
Pullup is disabled for port B bit 4.
#0
1
Pullup is enabled for port B bit 4.
#1
PTBPE5
Pull Enable for Port B Bit 5
13
1
read-write
0
Pullup is disabled for port B bit 5.
#0
1
Pullup is enabled for port B bit 5.
#1
PTBPE6
Pull Enable for Port B Bit 6
14
1
read-write
0
Pullup is disabled for port B bit 6.
#0
1
Pullup is enabled for port B bit 6.
#1
PTBPE7
Pull Enable for Port B Bit 7
15
1
read-write
0
Pullup is disabled for port B bit 7.
#0
1
Pullup is enabled for port B bit 7.
#1
PTCPE0
Pull Enable for Port C Bit 0
16
1
read-write
0
Pullup is disabled for port C bit 0.
#0
1
Pullup is enabled for port C bit 0.
#1
PTCPE1
Pull Enable for Port C Bit 1
17
1
read-write
0
Pullup is disabled for port C bit 1.
#0
1
Pullup is enabled for port C bit 1.
#1
PTCPE2
Pull Enable for Port C Bit 2
18
1
read-write
0
Pullup is disabled for port C bit 2.
#0
1
Pullup is enabled for port C bit 2.
#1
PTCPE3
Pull Enable for Port C Bit 3
19
1
read-write
0
Pullup is disabled for port C bit 3.
#0
1
Pullup is enabled for port C bit 3.
#1
PTCPE4
Pull Enable for Port C Bit 4
20
1
read-write
0
Pullup is disabled for port C bit 4.
#0
1
Pullup is enabled for port C bit 4.
#1
PTCPE5
Pull Enable for Port C Bit 5
21
1
read-write
0
Pullup is disabled for port C bit 5.
#0
1
Pullup is enabled for port C bit 5.
#1
PTCPE6
Pull Enable for Port C Bit 6
22
1
read-write
0
Pullup is disabled for port C bit 6.
#0
1
Pullup is enabled for port C bit 6.
#1
PTCPE7
Pull Enable for Port C Bit 7
23
1
read-write
0
Pullup is disabled for port C bit 7.
#0
1
Pullup is enabled for port C bit 7.
#1
PTDPE0
Pull Enable for Port D Bit 0
24
1
read-write
0
Pullup is disabled for port D bit 0.
#0
1
Pullup is enabled for port D bit 0.
#1
PTDPE1
Pull Enable for Port D Bit 1
25
1
read-write
0
Pullup is disabled for port D bit 1.
#0
1
Pullup is enabled for port D bit 1.
#1
PTDPE2
Pull Enable for Port D Bit 2
26
1
read-write
0
Pullup is disabled for port D bit 2.
#0
1
Pullup is enabled for port D bit 2.
#1
PTDPE3
Pull Enable for Port D Bit 3
27
1
read-write
0
Pullup is disabled for port D bit 3.
#0
1
Pullup is enabled for port D bit 3.
#1
PTDPE4
Pull Enable for Port D Bit 4
28
1
read-write
0
Pullup is disabled for port D bit 4.
#0
1
Pullup is enabled for port D bit 4.
#1
PTDPE5
Pull Enable for Port D Bit 5
29
1
read-write
0
Pullup is disabled for port D bit 5.
#0
1
Pullup is enabled for port D bit 5.
#1
PTDPE6
Pull Enable for Port D Bit 6
30
1
read-write
0
Pullup is disabled for port D bit 6.
#0
1
Pullup is enabled for port D bit 6.
#1
PTDPE7
Pull Enable for Port D Bit 7
31
1
read-write
0
Pullup is disabled for port D bit 7.
#0
1
Pullup is enabled for port D bit 7.
#1
PTA
General Purpose Input/Output
GPIO
0x0
0x0
0x1C
registers
n
GPIOA_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
GPIOA_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOA_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
GPIOA_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOA_PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
GPIOA_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
GPIOA_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PTB
General Purpose Input/Output
GPIO
0x0
0x0
0x1C
registers
n
GPIOB_PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
GPIOB_PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
GPIOB_PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
GPIOB_PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOB_PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
GPIOB_PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
GPIOB_PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
PCOR
Port Clear Output Register
0x8
32
write-only
n
0x0
0x0
PTCO
Port Clear Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is cleared to logic 0.
#1
PDDR
Port Data Direction Register
0x14
32
read-write
n
0x0
0x0
PDD
Port Data Direction
0
32
read-write
0
Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
32
read-only
n
0x0
0x0
PDI
Port Data Input
0
32
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
32
read-write
n
0x0
0x0
PDO
Port Data Output
0
32
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
PIDR
Port Input Disable Register
0x18
32
read-write
n
0x0
0x0
PID
Port Input Disable
0
32
read-write
0
Pin is configured for General Purpose Input, provided the pin is configured for any digital function.
#0
1
Pin is not configured as General Purpose Input.Corresponding Pin Data Input Register bit will read zero.
#1
PSOR
Port Set Output Register
0x4
32
write-only
n
0x0
0x0
PTSO
Port Set Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to logic 1.
#1
PTOR
Port Toggle Output Register
0xC
32
write-only
n
0x0
0x0
PTTO
Port Toggle Output
0
32
write-only
0
Corresponding bit in PDORn does not change.
#0
1
Corresponding bit in PDORn is set to the inverse of its existing logic state.
#1
ROM
System ROM
ROM
0x0
0x0
0x1000
registers
n
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
ENTRY
Entry
0x0
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
no description available
0
32
read-only
SYSACCESS
System Access Register
0xFCC
32
read-only
n
0x0
0x0
SYSACCESS
no description available
0
32
read-only
TABLEMARK
End of Table Marker Register
0x4
32
read-only
n
0x0
0x0
MARK
no description available
0
32
read-only
RTC
Real-time counter
RTC
0x0
0x0
0xC
registers
n
RTC
4
INT_RTC
20
CNT
RTC Counter Register
0x8
32
read-only
n
0x0
0x0
CNT
RTC Count
0
16
read-only
RESERVED
no description available
16
16
read-only
MOD
RTC Modulo Register
0x4
32
read-write
n
0x0
0x0
MOD
RTC Modulo
0
16
read-write
RESERVED
no description available
16
16
read-only
SC
RTC Status and Control Register
0x0
32
read-write
n
0x0
0x0
RESERVED
no description available
0
4
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
11
3
read-only
RESERVED
no description available
16
16
read-only
RTCLKS
Real-Time Clock Source Select
14
2
read-write
00
External clock source.
#00
01
Real-time clock source is 1 kHz.
#01
10
Internal clock.
#10
11
Bus clock.
#11
RTCO
Real-Time Counter Output
4
1
read-write
0
Real-time counter output disabled.
#0
1
Real-time counter output enabled.
#1
RTCPS
Real-Time Clock Prescaler Select
8
3
read-write
000
Off
#000
001
If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128.
#001
010
If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256.
#010
011
If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512.
#011
100
If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024.
#100
101
If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048.
#101
110
If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100.
#110
111
If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000.
#111
RTIE
Real-Time Interrupt Enable
6
1
read-write
0
Real-time interrupt requests are disabled. Use software polling.
#0
1
Real-time interrupt requests are enabled.
#1
RTIF
Real-Time Interrupt Flag
7
1
read-write
0
RTC counter has not reached the value in the RTC modulo register.
#0
1
RTC counter has reached the value in the RTC modulo register.
#1
SIM
System Integration Module
SIM
0x0
0x0
0x1C
registers
n
BUSDIV
BUS Clock Divider Register
0x18
32
read-write
n
0x0
0x0
BUSDIV
BUS Clock Divider
0
1
read-write
0
Bus clock is same as ICSOUTCLK.
#0
1
Bus clock is ICSOUTCLK divided by 2.
#1
RESERVED
no description available
1
31
read-only
PINSEL
Pin Selection Register
0x8
32
read-write
n
0x0
0x0
FTM0PS0
FTM0[0] Port Pin Select
8
1
read-write
0
FTM0[0] channels are mapped on PTA0.
#0
1
FTM0[0] channels are mapped on PTB2.
#1
FTM0PS1
FTM0[1] Port Pin Select
9
1
read-write
0
FTM0[1] channels are mapped on PTA1.
#0
1
FTM0[1] channels are mapped on PTB3.
#1
FTM1PS0
FTM1[0] Port Pin Select
10
1
read-write
0
FTM1[0] channels are mapped on PTC4.
#0
1
FTM1[0] channels are mapped on PTH2.
#1
FTM1PS1
FTM1[1] Port Pin Select
11
1
read-write
0
FTM1[1] channels are mapped on PTC5.
#0
1
FTM1[1] channels are mapped on PTE7.
#1
FTM2PS0
FTM2[0] Port Pin Select
12
1
read-write
0
FTM2[0] channels are mapped on PTC0.
#0
1
FTM2[0] channels are mapped on PTH0.
#1
FTM2PS1
FTM2[1] Port Pin Select
13
1
read-write
0
FTM2[1] channels are mapped on PTC1.
#0
1
FTM2[1] channels are mapped on PTH1.
#1
FTM2PS2
FTM2[2] Port Pin Select
14
1
read-write
0
FTM2[2] channels are mapped on PTC2.
#0
1
FTM2[2] channels are mapped on PTD0.
#1
FTM2PS3
FTM2[3] Port Pin Select
15
1
read-write
0
FTM2[3] channels are mapped on PTC3.
#0
1
FTM2[3] channels are mapped on PTD1.
#1
I2C0PS
I2C0 Port Pin Select
5
1
read-write
0
I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively.
#0
1
I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively.
#1
IICPS
IIC Port Pin Select
5
1
read-write
0
I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively.
#0
1
I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively.
#1
RESERVED
no description available
0
4
read-only
RESERVED
no description available
16
16
read-only
RTCPS
RTCO Pin Select
4
1
read-write
0
RTCO is mapped on PTC4.
#0
1
RTCO is mapped on PTC5.
#1
SPI0PS
SPI0 Pin Select
6
1
read-write
0
SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTB2, PTB3, PTB4, and PTB5.
#0
1
SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS0 are mapped on PTE0, PTE1, PTE2, and PTE3.
#1
UART0PS
UART0 Pin Select
7
1
read-write
0
UART0_RX and UART0_TX are mapped on PTB0 and PTB1.
#0
1
UART0_RX and UART0_TX are mapped on PTA2 and PTA3.
#1
SCGC
System Clock Gating Control Register
0xC
32
read-write
n
0x0
0x0
ACMP0
ACMP0 Clock Gate Control
30
1
read-write
0
Bus clock to the ACMP0 module is disabled.
#0
1
Bus clock to the ACMP0 module is enabled.
#1
ACMP1
ACMP1 Clock Gate Control
31
1
read-write
0
Bus clock to the ACMP1 module is disabled.
#0
1
Bus clock to the ACMP1 module is enabled.
#1
ADC
ADC Clock Gate Control
29
1
read-write
0
Bus clock to the ADC module is disabled.
#0
1
Bus clock to the ADC module is enabled.
#1
CRC
CRC Clock Gate Control
10
1
read-write
0
Bus clock to the CRC module is disabled.
#0
1
Bus clock to the CRC module is enabled.
#1
FLASH
Flash Clock Gate Control
12
1
read-write
0
Bus clock to the flash module is disabled.
#0
1
Bus clock to the flash module is enabled.
#1
FTM0
FTM0 Clock Gate Control
5
1
read-write
0
Bus clock to the FTM0 module is disabled.
#0
1
Bus clock to the FTM0 module is enabled.
#1
FTM1
FTM1 Clock Gate Control
6
1
read-write
0
Bus clock to the FTM1 module is disabled.
#0
1
Bus clock to the FTM1 module is enabled.
#1
FTM2
FTM2 Clock Gate Control
7
1
read-write
0
Bus clock to the FTM2 module is disabled.
#0
1
Bus clock to the FTM2 module is enabled.
#1
I2C
I2C Clock Gate Control
17
1
read-write
0
Bus clock to the IIC module is disabled.
#0
1
Bus clock to the IIC module is enabled.
#1
IIC
IIC Clock Gate Control
17
1
read-write
0
Bus clock to the IIC module is disabled.
#0
1
Bus clock to the IIC module is enabled.
#1
IRQ
IRQ Clock Gate Control
27
1
read-write
0
Bus clock to the IRQ module is disabled.
#0
1
Bus clock to the IRQ module is enabled.
#1
KBI0
KBI0 Clock Gate Control
24
1
read-write
0
Bus clock to the KBI0 module is disabled.
#0
1
Bus clock to the KBI0 module is enabled.
#1
KBI1
KBI1 Clock Gate Control
25
1
read-write
0
Bus clock to the KBI1 module is disabled.
#0
1
Bus clock to the KBI1 module is enabled.
#1
PIT
PIT Clock Gate Control
1
1
read-write
0
Bus clock to the PIT module is disabled.
#0
1
Bus clock to the PIT module is enabled.
#1
RESERVED
no description available
2
3
read-only
RESERVED
no description available
8
2
read-only
RESERVED
no description available
11
1
read-only
RESERVED
no description available
14
3
read-only
RESERVED
no description available
23
1
read-only
RESERVED
no description available
26
1
read-only
RESERVED
no description available
28
1
read-only
RTC
RTC Clock Gate Control
0
1
read-write
0
Bus clock to the RTC module is disabled.
#0
1
Bus clock to the RTC module is enabled.
#1
SPI0
SPI0 Clock Gate Control
18
1
read-write
0
Bus clock to the SPI0 module is disabled.
#0
1
Bus clock to the SPI0 module is enabled.
#1
SPI1
SPI1 Clock Gate Control
19
1
read-write
0
Bus clock to the SPI1 module is disabled.
#0
1
Bus clock to the SPI1 module is enabled.
#1
SWD
SWD (single wire debugger) Clock Gate Control
13
1
read-write
0
Bus clock to the SWD module is disabled.
#0
1
Bus clock to the SWD module is enabled.
#1
UART0
UART0 Clock Gate Control
20
1
read-write
0
Bus clock to the UART0 module is disabled.
#0
1
Bus clock to the UART0 module is enabled.
#1
UART1
UART1 Clock Gate Control
21
1
read-write
0
Bus clock to the UART1 module is disabled.
#0
1
Bus clock to the UART1 module is enabled.
#1
UART2
UART2 Clock Gate Control
22
1
read-write
0
Bus clock to the UART2 module is disabled.
#0
1
Bus clock to the UART2 module is enabled.
#1
SOPT
System Options Register
0x4
32
read-write
n
0x0
0x0
ACIC
Analog Comparator to Input Capture Enable
11
1
read-write
0
ACMP0 output is not connected to FTM1 input channel 0.
#0
1
ACMP0 output is connected to FTM1 input channel 0.
#1
ADHWT
ADC Hardware Trigger Source
8
2
read-write
00
RTC overflow as the ADC hardware trigger
#00
01
PIT overflow as the ADC hardware trigger
#01
10
FTM2 init trigger with 8-bit programmable delay
#10
11
FTM2 match trigger with 8-bit programmable delay
#11
BUSREF
BUS Clock Output select
16
3
read-write
000
Bus
#000
001
Bus divided by 2
#001
010
Bus divided by 4
#010
011
Bus divided by 8
#011
100
Bus divided by 16
#100
101
Bus divided by 32
#101
110
Bus divided by 64
#110
111
Bus divided by 128
#111
CLKOE
Bus Clock Output Enable
19
1
read-write
0
Bus clock output is disabled on PTH2.
#0
1
Bus clock output is enabled on PTH2.
#1
DELAY
FTM2 Trigger Delay
24
8
read-write
DLYACT
FTM2 Trigger Delay Active
23
1
read-only
0
The delay is inactive.
#0
1
The delay is active.
#1
FTMSYNC
FTM2 Synchronization Select
14
1
write-only
0
No synchronization triggered.
#0
1
Generates a PWM synchronization trigger to the FTM2 modules.
#1
NMIE
NMI Pin Enable
1
1
read-write
0
PTB4/FTM2_CH4/SPI0_MISO/NMI_b/ACMP1_IN2 pin functions as PTB4, FTM2_CH4, SPI0_MISO, or ACMP1_IN2.
#0
1
PTB4/FTM2_CH4/SPI0_MISO/NMI_b/ACMP1_IN2 pin functions as NMI_b.
#1
RESERVED
no description available
0
1
read-only
RESERVED
no description available
4
4
read-only
RESERVED
no description available
20
3
read-only
RSTPE
RESET Pin Enable
2
1
read-write
0
PTA5/IRQ/FTM0_CLK/RESET_b pin functions as PTA5, IRQ, or FTM0_CLK.
#0
1
PTA5/IRQ/FTM0_CLK/RESET_b pin functions as RESET_b.
#1
RTCC
Real-Time Counter Capture
10
1
read-write
0
RTC overflow is not connected to FTM1 input channel 1.
#0
1
RTC overflow is connected to FTM1 input channel 1.
#1
RXDCE
UART0_RX Capture Select
12
1
read-write
0
UART0_RX input signal is connected to the UART0 module only.
#0
1
UART0_RX input signal is connected to the UART0 module and FTM0 channel 1.
#1
RXDFE
UART0_RX Filter Select
13
1
read-write
0
UART0_RX input signal is connected to UART0 module directly.
#0
1
UART0_RX input signal is filtered by ACMP, then injected to UART0.
#1
SWDE
Single Wire Debug Port Pin Enable
3
1
read-write
0
PTA4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/RTCO/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, RTCO, FTM1_CH0, or ACMP0_IN2 function.
#0
1
PTA4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/RTCO/FTM1CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function.
#1
TXDME
UART0_TX Modulation Select
15
1
read-write
0
UART0_TX output is connected to pinout directly.
#0
1
UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout.
#1
SRSID
System Reset Status and ID Register
0x0
32
read-only
n
0x0
0x0
FAMID
Kinetis family ID
28
4
read-only
0000
KE0x family.
#0000
LOC
Internal Clock Source Module Reset
2
1
read-only
0
Reset is not caused by the ICS module.
#0
1
Reset is caused by the ICS module.
#1
LOCKUP
Core Lockup
9
1
read-only
0
Reset is not caused by core LOCKUP event.
#0
1
Reset is caused by core LOCKUP event.
#1
LVD
Low Voltage Detect
1
1
read-only
0
Reset is not caused by LVD trip or POR.
#0
1
Reset is caused by LVD trip or POR.
#1
MDMAP
MDM-AP System Reset Request
11
1
read-only
0
Reset is not caused by host debugger system setting of the System Reset Request bit.
#0
1
Reset is caused by host debugger system setting of the System Reset Request bit.
#1
PIN
External Reset Pin
6
1
read-only
0
Reset is not caused by external reset pin.
#0
1
Reset came from external reset pin.
#1
PINID
Device Pin ID
16
4
read-only
0000
8-pin
#0000
0001
16-pin
#0001
0010
20-pin
#0010
0011
24-pin
#0011
0100
32-pin
#0100
0101
44-pin
#0101
0110
48-pin
#0110
0111
64-pin
#0111
1000
80-pin
#1000
1010
100-pin
#1010
POR
Power-On Reset
7
1
read-only
0
Reset not caused by POR.
#0
1
POR caused reset.
#1
RESERVED
no description available
0
1
read-only
RESERVED
no description available
3
2
read-only
RESERVED
no description available
8
1
read-only
RESERVED
no description available
12
1
read-only
RESERVED
no description available
14
2
read-only
RevID
Device Revision Number
20
4
read-only
SACKERR
Stop Mode Acknowledge Error Reset
13
1
read-only
0
Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode.
#0
1
Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode.
#1
SUBFAMID
Kinetis sub-family ID
24
4
read-only
0010
KEx2 sub-family
#0010
SW
Software
10
1
read-only
0
Reset is not caused by software setting of SYSRESETREQ bit.
#0
1
Reset caused by software setting of SYSRESETREQ bit
#1
WDOG
Watchdog (WDOG)
5
1
read-only
0
Reset is not caused by WDOG timeout.
#0
1
Reset is caused by WDOG timeout.
#1
UUIDH
Universally Unique Identifier High Register
0x14
32
read-only
n
0x0
0x0
ID
Universally Unique Identifier
0
32
read-only
UUIDL
Universally Unique Identifier Low Register
0x10
32
read-only
n
0x0
0x0
ID
Universally Unique Identifier
0
32
read-only
SPI0
Serial Peripheral Interface
SPI
0x0
0x0
0x8
registers
n
SPI0
10
INT_SPI0
10
BR
SPI baud rate register
0x2
8
read-write
n
0x0
0x0
RESERVED
no description available
7
1
read-only
SPPR
SPI baud rate prescale divisor
4
3
read-write
000
Baud rate prescaler divisor is 1
#000
001
Baud rate prescaler divisor is 2
#001
010
Baud rate prescaler divisor is 3
#010
011
Baud rate prescaler divisor is 4
#011
100
Baud rate prescaler divisor is 5
#100
101
Baud rate prescaler divisor is 6
#101
110
Baud rate prescaler divisor is 7
#110
111
Baud rate prescaler divisor is 8
#111
SPR
SPI baud rate divisor
0
4
read-write
0000
Baud rate divisor is 2
#0000
0001
Baud rate divisor is 4
#0001
0010
Baud rate divisor is 8
#0010
0011
Baud rate divisor is 16
#0011
0100
Baud rate divisor is 32
#0100
0101
Baud rate divisor is 64
#0101
0110
Baud rate divisor is 128
#0110
0111
Baud rate divisor is 256
#0111
1000
Baud rate divisor is 512
#1000
C1
SPI control register 1
0x0
8
read-write
n
0x0
0x0
CPHA
Clock phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer
#1
CPOL
Clock polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB first (shifter direction)
0
1
read-write
0
SPI serial data transfers start with most significant bit
#0
1
SPI serial data transfers start with least significant bit
#1
MSTR
Master/slave mode select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI system enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI interrupt enable: for SPRF and MODF
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling
#0
1
Request a hardware interrupt when SPRF or MODF is 1
#1
SPTIE
SPI transmit interrupt enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave select output enable
1
1
read-write
0
When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI control register 2
0x1
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional mode output enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master mode-fault function enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RESERVED
no description available
2
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
SPC0
SPI pin control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPISWAI
SPI stop in wait mode
1
1
read-write
0
SPI clocks continue to operate in wait mode
#0
1
SPI clocks stop when the MCU enters wait mode
#1
SPMIE
SPI match interrupt enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
D
SPI data register
0x5
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
M
SPI match register
0x7
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI status register
0x3
8
read-only
n
0x0
0x0
MODF
Master mode fault flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
RESERVED
no description available
0
4
read-only
SPMF
SPI match flag
6
1
read-only
0
Value in the receive data buffer does not match the value in the M register
#0
1
Value in the receive data buffer matches the value in the M register
#1
SPRF
SPI read buffer full flag
7
1
read-only
0
No data available in the receive data buffer
#0
1
Data available in the receive data buffer
#1
SPTEF
SPI transmit buffer empty flag
5
1
read-only
0
SPI transmit buffer not empty
#0
1
SPI transmit buffer empty
#1
SPI1
Serial Peripheral Interface
SPI
0x0
0x0
0x8
registers
n
SPI1
11
INT_SPI1
11
BR
SPI baud rate register
0x2
8
read-write
n
0x0
0x0
RESERVED
no description available
7
1
read-only
SPPR
SPI baud rate prescale divisor
4
3
read-write
000
Baud rate prescaler divisor is 1
#000
001
Baud rate prescaler divisor is 2
#001
010
Baud rate prescaler divisor is 3
#010
011
Baud rate prescaler divisor is 4
#011
100
Baud rate prescaler divisor is 5
#100
101
Baud rate prescaler divisor is 6
#101
110
Baud rate prescaler divisor is 7
#110
111
Baud rate prescaler divisor is 8
#111
SPR
SPI baud rate divisor
0
4
read-write
0000
Baud rate divisor is 2
#0000
0001
Baud rate divisor is 4
#0001
0010
Baud rate divisor is 8
#0010
0011
Baud rate divisor is 16
#0011
0100
Baud rate divisor is 32
#0100
0101
Baud rate divisor is 64
#0101
0110
Baud rate divisor is 128
#0110
0111
Baud rate divisor is 256
#0111
1000
Baud rate divisor is 512
#1000
C1
SPI control register 1
0x0
8
read-write
n
0x0
0x0
CPHA
Clock phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer
#1
CPOL
Clock polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB first (shifter direction)
0
1
read-write
0
SPI serial data transfers start with most significant bit
#0
1
SPI serial data transfers start with least significant bit
#1
MSTR
Master/slave mode select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI system enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI interrupt enable: for SPRF and MODF
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling
#0
1
Request a hardware interrupt when SPRF or MODF is 1
#1
SPTIE
SPI transmit interrupt enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave select output enable
1
1
read-write
0
When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI control register 2
0x1
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional mode output enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master mode-fault function enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RESERVED
no description available
2
1
read-only
RESERVED
no description available
5
1
read-only
RESERVED
no description available
6
1
read-only
SPC0
SPI pin control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPISWAI
SPI stop in wait mode
1
1
read-write
0
SPI clocks continue to operate in wait mode
#0
1
SPI clocks stop when the MCU enters wait mode
#1
SPMIE
SPI match interrupt enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
D
SPI data register
0x5
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
M
SPI match register
0x7
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI status register
0x3
8
read-only
n
0x0
0x0
MODF
Master mode fault flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
RESERVED
no description available
0
4
read-only
SPMF
SPI match flag
6
1
read-only
0
Value in the receive data buffer does not match the value in the M register
#0
1
Value in the receive data buffer matches the value in the M register
#1
SPRF
SPI read buffer full flag
7
1
read-only
0
No data available in the receive data buffer
#0
1
Data available in the receive data buffer
#1
SPTEF
SPI transmit buffer empty flag
5
1
read-only
0
SPI transmit buffer not empty
#0
1
SPI transmit buffer empty
#1
SystemControl
System Control Registers
SystemControl
0x0
0x8
0xD2C
registers
n
SCB_ACTLR
Auxiliary Control Register,
0x8
32
read-only
n
0x0
0x0
SCB_AIRCR
Application Interrupt and Reset Control Register
0xD0C
32
read-write
n
0x0
0x0
ENDIANNESS
no description available
15
1
read-only
0
Little-endian
#0
1
Big-endian
#1
SYSRESETREQ
no description available
2
1
write-only
0
no system reset request
#0
1
asserts a signal to the outer system that requests a reset
#1
VECTCLRACTIVE
no description available
1
1
write-only
VECTKEY
Register key
16
16
read-write
SCB_CCR
Configuration and Control Register
0xD14
32
read-only
n
0x0
0x0
STKALIGN
Indicates stack alignment on exception entry
9
1
read-only
UNALIGN_TRP
Always reads as one, indicates that all unaligned accesses generate a HardFault
3
1
read-only
SCB_CPUID
CPUID Base Register
0xD00
32
read-only
n
0x0
0x0
IMPLEMENTER
Implementer code
24
8
read-only
PARTNO
Indicates part number
4
12
read-only
REVISION
Indicates patch release: 0x0 = Patch 0
0
4
read-only
VARIANT
Indicates processor revision: 0x2 = Revision 2
20
4
read-only
SCB_DFSR
Debug Fault Status Register
0xD30
32
read-write
n
0x0
0x0
BKPT
no description available
1
1
read-write
0
No current breakpoint debug event
#0
1
At least one current breakpoint debug event
#1
DWTTRAP
no description available
2
1
read-write
0
No current debug events generated by the DWT
#0
1
At least one current debug event generated by the DWT
#1
EXTERNAL
no description available
4
1
read-write
0
No EDBGRQ debug event
#0
1
EDBGRQ debug event
#1
HALTED
no description available
0
1
read-write
0
No active halt request debug event
#0
1
Halt request debug event active
#1
VCATCH
no description available
3
1
read-write
0
No Vector catch triggered
#0
1
Vector catch triggered
#1
SCB_ICSR
Interrupt Control and State Register
0xD04
32
read-write
n
0x0
0x0
ISRPENDING
no description available
22
1
read-only
NMIPENDSET
no description available
31
1
read-write
0
write: no effect; read: NMI exception is not pending
#0
1
write: changes NMI exception state to pending; read: NMI exception is pending
#1
PENDSTCLR
no description available
25
1
write-only
0
no effect
#0
1
removes the pending state from the SysTick exception
#1
PENDSTSET
no description available
26
1
read-write
0
write: no effect; read: SysTick exception is not pending
#0
1
write: changes SysTick exception state to pending; read: SysTick exception is pending
#1
PENDSVCLR
no description available
27
1
write-only
0
no effect
#0
1
removes the pending state from the PendSV exception
#1
PENDSVSET
no description available
28
1
read-write
0
write: no effect; read: PendSV exception is not pending
#0
1
write: changes PendSV exception state to pending; read: PendSV exception is pending
#1
VECTACTIVE
Active exception number
0
6
read-only
VECTPENDING
Exception number of the highest priority pending enabled exception
12
6
read-only
SCB_SCR
System Control Register
0xD10
32
read-write
n
0x0
0x0
SEVONPEND
no description available
4
1
read-write
0
only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
#0
1
enabled events and all interrupts, including disabled interrupts, can wakeup the processor
#1
SLEEPDEEP
no description available
2
1
read-write
0
sleep
#0
1
deep sleep
#1
SLEEPONEXIT
no description available
1
1
read-write
0
o not sleep when returning to Thread mode
#0
1
enter sleep, or deep sleep, on return from an ISR
#1
SCB_SHCSR
System Handler Control and State Register
0xD24
32
read-write
n
0x0
0x0
SVCALLPENDED
no description available
15
1
read-write
0
exception is not pending
#0
1
exception is pending
#1
SCB_SHPR2
System Handler Priority Register 2
0xD1C
32
read-write
n
0x0
0x0
PRI_11
Priority of system handler 11, SVCall
24
8
read-write
SCB_SHPR3
System Handler Priority Register 3
0xD20
32
read-write
n
0x0
0x0
PRI_14
Priority of system handler 14, PendSV
16
8
read-write
PRI_15
Priority of system handler 15, SysTick exception
24
8
read-write
SCB_VTOR
Vector Table Offset Register
0xD08
32
read-write
n
0x0
0x0
TBLOFF
Vector table base offset
7
25
read-write
SysTick
System timer
SysTick
0x0
0x0
0x10
registers
n
SYST_CALIB
SysTick Calibration Value Register
0xC
32
read-only
n
0x0
0x0
NOREF
no description available
31
1
read-only
0
The reference clock is provided
#0
1
The reference clock is not provided
#1
SKEW
no description available
30
1
read-only
0
10ms calibration value is exact
#0
1
10ms calibration value is inexact, because of the clock frequency
#1
TENMS
Reload value to use for 10ms timing
0
24
read-only
SYST_CSR
SysTick Control and Status Register
0x0
32
read-write
n
0x0
0x0
CLKSOURCE
no description available
2
1
read-write
0
external clock
#0
1
processor clock
#1
COUNTFLAG
no description available
16
1
read-write
ENABLE
no description available
0
1
read-write
0
counter disabled
#0
1
counter enabled
#1
TICKINT
no description available
1
1
read-write
0
counting down to 0 does not assert the SysTick exception request
#0
1
counting down to 0 asserts the SysTick exception request
#1
SYST_CVR
SysTick Current Value Register
0x8
32
read-write
n
0x0
0x0
CURRENT
Current value at the time the register is accessed
0
24
read-write
SYST_RVR
SysTick Reload Value Register
0x4
32
read-write
n
0x0
0x0
RELOAD
Value to load into the SysTick Current Value Register when the counter reaches 0
0
24
read-write
UART0
Universal Asynchronous Receiver/Transmitter (UART)
UART
0x0
0x0
0x8
registers
n
UART0
12
INT_UART0
12
BDH
UART Baud Rate Register: High
0x0
8
read-write
n
0x0
0x0
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
7
1
read-write
0
Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
6
1
read-write
0
Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
#1
SBNS
Stop Bit Number Select
5
1
read-write
0
One stop bit.
#0
1
Two stop bit.
#1
SBR
Baud Rate Modulo Divisor.
0
5
read-write
BDL
UART Baud Rate Register: Low
0x1
8
read-write
n
0x0
0x0
SBR
Baud Rate Modulo Divisor
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation - RxD and TxD use separate pins.
#0
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.
#1
M
9-Bit or 8-Bit Mode Select
4
1
read-write
0
Normal - start + 8 data bits (lsb first) + stop.
#0
1
Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
#1
PE
Parity Enable
1
1
read-write
0
No hardware parity generation or checking.
#0
1
Parity enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
#0
1
Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU.
#0
1
UART clocks freeze while CPU is in wait mode.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle-line wakeup.
#0
1
Address-mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable for IDLE
4
1
read-write
0
Hardware interrupts from IDLE disabled; use polling.
#0
1
Hardware interrupt requested when IDLE flag is 1.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Interrupt Enable for RDRF
5
1
read-write
0
Hardware interrupts from RDRF disabled; use polling.
#0
1
Hardware interrupt requested when RDRF flag is 1.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal UART receiver operation.
#0
1
UART receiver in standby waiting for wakeup condition.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break character(s) to be sent.
#1
TCIE
Transmission Complete Interrupt Enable for TC
6
1
read-write
0
Hardware interrupts from TC disabled; use polling.
#0
1
Hardware interrupt requested when TC flag is 1.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmit Interrupt Enable for TDRE
7
1
read-write
0
Hardware interrupts from TDRE disabled; use polling.
#0
1
Hardware interrupt requested when TDRE flag is 1.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupts disabled; use polling).
#0
1
Hardware interrupt requested when FE is set.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when NF is set.
#1
ORIE
Overrun Interrupt Enable
3
1
read-write
0
OR interrupts disabled; use polling.
#0
1
Hardware interrupt requested when OR is set.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when PF is set.
#1
R8
Ninth Data Bit for Receiver
7
1
read-only
T8
Ninth Data Bit for Transmitter
6
1
read-write
TXDIR
TxD Pin Direction in Single-Wire Mode
5
1
read-write
0
TxD pin is an input in single-wire mode.
#0
1
TxD pin is an output in single-wire mode.
#1
TXINV
Transmit Data Inversion
4
1
read-write
0
Transmit data not inverted.
#0
1
Transmit data inverted.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
R0T0
no description available
0
1
read-write
R1T1
no description available
1
1
read-write
R2T2
no description available
2
1
read-write
R3T3
no description available
3
1
read-write
R4T4
no description available
4
1
read-write
R5T5
no description available
5
1
read-write
R6T6
no description available
6
1
read-write
R7T7
no description available
7
1
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected. This does not guarantee the framing is correct.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
No idle line detected.
#0
1
Idle line was detected.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected.
#0
1
Noise detected in the received character in UART_D.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun.
#0
1
Receive overrun (new UART data lost).
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error.
#0
1
Parity error.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
Receive data register empty.
#0
1
Receive data register full.
#1
TC
Transmission Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
Transmit data register (buffer) full.
#0
1
Transmit data register (buffer) empty.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Character Generation Length
2
1
read-write
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#0
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#0
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character has been detected.
#0
1
LIN break character has been detected.
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle waiting for a start bit.
#0
1
UART receiver active (RxD input not idle).
#1
RESERVED
no description available
5
1
read-only
RWUID
Receive Wake Up Idle Detect
3
1
read-write
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
#0
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data not inverted.
#0
1
Receive data inverted.
#1
UART1
Universal Asynchronous Receiver/Transmitter (UART)
UART
0x0
0x0
0x8
registers
n
UART1
13
INT_UART1
13
BDH
UART Baud Rate Register: High
0x0
8
read-write
n
0x0
0x0
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
7
1
read-write
0
Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
6
1
read-write
0
Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
#1
SBNS
Stop Bit Number Select
5
1
read-write
0
One stop bit.
#0
1
Two stop bit.
#1
SBR
Baud Rate Modulo Divisor.
0
5
read-write
BDL
UART Baud Rate Register: Low
0x1
8
read-write
n
0x0
0x0
SBR
Baud Rate Modulo Divisor
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation - RxD and TxD use separate pins.
#0
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.
#1
M
9-Bit or 8-Bit Mode Select
4
1
read-write
0
Normal - start + 8 data bits (lsb first) + stop.
#0
1
Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
#1
PE
Parity Enable
1
1
read-write
0
No hardware parity generation or checking.
#0
1
Parity enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
#0
1
Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU.
#0
1
UART clocks freeze while CPU is in wait mode.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle-line wakeup.
#0
1
Address-mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable for IDLE
4
1
read-write
0
Hardware interrupts from IDLE disabled; use polling.
#0
1
Hardware interrupt requested when IDLE flag is 1.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Interrupt Enable for RDRF
5
1
read-write
0
Hardware interrupts from RDRF disabled; use polling.
#0
1
Hardware interrupt requested when RDRF flag is 1.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal UART receiver operation.
#0
1
UART receiver in standby waiting for wakeup condition.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break character(s) to be sent.
#1
TCIE
Transmission Complete Interrupt Enable for TC
6
1
read-write
0
Hardware interrupts from TC disabled; use polling.
#0
1
Hardware interrupt requested when TC flag is 1.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmit Interrupt Enable for TDRE
7
1
read-write
0
Hardware interrupts from TDRE disabled; use polling.
#0
1
Hardware interrupt requested when TDRE flag is 1.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupts disabled; use polling).
#0
1
Hardware interrupt requested when FE is set.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when NF is set.
#1
ORIE
Overrun Interrupt Enable
3
1
read-write
0
OR interrupts disabled; use polling.
#0
1
Hardware interrupt requested when OR is set.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when PF is set.
#1
R8
Ninth Data Bit for Receiver
7
1
read-only
T8
Ninth Data Bit for Transmitter
6
1
read-write
TXDIR
TxD Pin Direction in Single-Wire Mode
5
1
read-write
0
TxD pin is an input in single-wire mode.
#0
1
TxD pin is an output in single-wire mode.
#1
TXINV
Transmit Data Inversion
4
1
read-write
0
Transmit data not inverted.
#0
1
Transmit data inverted.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
R0T0
no description available
0
1
read-write
R1T1
no description available
1
1
read-write
R2T2
no description available
2
1
read-write
R3T3
no description available
3
1
read-write
R4T4
no description available
4
1
read-write
R5T5
no description available
5
1
read-write
R6T6
no description available
6
1
read-write
R7T7
no description available
7
1
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected. This does not guarantee the framing is correct.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
No idle line detected.
#0
1
Idle line was detected.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected.
#0
1
Noise detected in the received character in UART_D.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun.
#0
1
Receive overrun (new UART data lost).
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error.
#0
1
Parity error.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
Receive data register empty.
#0
1
Receive data register full.
#1
TC
Transmission Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
Transmit data register (buffer) full.
#0
1
Transmit data register (buffer) empty.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Character Generation Length
2
1
read-write
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#0
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#0
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character has been detected.
#0
1
LIN break character has been detected.
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle waiting for a start bit.
#0
1
UART receiver active (RxD input not idle).
#1
RESERVED
no description available
5
1
read-only
RWUID
Receive Wake Up Idle Detect
3
1
read-write
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
#0
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data not inverted.
#0
1
Receive data inverted.
#1
UART2
Universal Asynchronous Receiver/Transmitter (UART)
UART
0x0
0x0
0x8
registers
n
UART2
14
INT_UART2
14
BDH
UART Baud Rate Register: High
0x0
8
read-write
n
0x0
0x0
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
7
1
read-write
0
Hardware interrupts from UART_S2[LBKDIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART_S2[LBKDIF] flag is 1.
#1
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
6
1
read-write
0
Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling).
#0
1
Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1.
#1
SBNS
Stop Bit Number Select
5
1
read-write
0
One stop bit.
#0
1
Two stop bit.
#1
SBR
Baud Rate Modulo Divisor.
0
5
read-write
BDL
UART Baud Rate Register: Low
0x1
8
read-write
n
0x0
0x0
SBR
Baud Rate Modulo Divisor
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation - RxD and TxD use separate pins.
#0
1
Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART.
#1
M
9-Bit or 8-Bit Mode Select
4
1
read-write
0
Normal - start + 8 data bits (lsb first) + stop.
#0
1
Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop.
#1
PE
Parity Enable
1
1
read-write
0
No hardware parity generation or checking.
#0
1
Parity enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins.
#0
1
Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input.
#1
UARTSWAI
UART Stops in Wait Mode
6
1
read-write
0
UART clocks continue to run in wait mode so the UART can be the source of an interrupt that wakes up the CPU.
#0
1
UART clocks freeze while CPU is in wait mode.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle-line wakeup.
#0
1
Address-mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable for IDLE
4
1
read-write
0
Hardware interrupts from IDLE disabled; use polling.
#0
1
Hardware interrupt requested when IDLE flag is 1.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Interrupt Enable for RDRF
5
1
read-write
0
Hardware interrupts from RDRF disabled; use polling.
#0
1
Hardware interrupt requested when RDRF flag is 1.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal UART receiver operation.
#0
1
UART receiver in standby waiting for wakeup condition.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break character(s) to be sent.
#1
TCIE
Transmission Complete Interrupt Enable for TC
6
1
read-write
0
Hardware interrupts from TC disabled; use polling.
#0
1
Hardware interrupt requested when TC flag is 1.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmit Interrupt Enable for TDRE
7
1
read-write
0
Hardware interrupts from TDRE disabled; use polling.
#0
1
Hardware interrupt requested when TDRE flag is 1.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupts disabled; use polling).
#0
1
Hardware interrupt requested when FE is set.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when NF is set.
#1
ORIE
Overrun Interrupt Enable
3
1
read-write
0
OR interrupts disabled; use polling.
#0
1
Hardware interrupt requested when OR is set.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupts disabled; use polling).
#0
1
Hardware interrupt requested when PF is set.
#1
R8
Ninth Data Bit for Receiver
7
1
read-only
T8
Ninth Data Bit for Transmitter
6
1
read-write
TXDIR
TxD Pin Direction in Single-Wire Mode
5
1
read-write
0
TxD pin is an input in single-wire mode.
#0
1
TxD pin is an output in single-wire mode.
#1
TXINV
Transmit Data Inversion
4
1
read-write
0
Transmit data not inverted.
#0
1
Transmit data inverted.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
R0T0
no description available
0
1
read-write
R1T1
no description available
1
1
read-write
R2T2
no description available
2
1
read-write
R3T3
no description available
3
1
read-write
R4T4
no description available
4
1
read-write
R5T5
no description available
5
1
read-write
R6T6
no description available
6
1
read-write
R7T7
no description available
7
1
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected. This does not guarantee the framing is correct.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
No idle line detected.
#0
1
Idle line was detected.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected.
#0
1
Noise detected in the received character in UART_D.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun.
#0
1
Receive overrun (new UART data lost).
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error.
#0
1
Parity error.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
Receive data register empty.
#0
1
Receive data register full.
#1
TC
Transmission Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
Transmit data register (buffer) full.
#0
1
Transmit data register (buffer) empty.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Character Generation Length
2
1
read-write
0
Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#0
1
Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1).
#1
LBKDE
LIN Break Detection Enable
1
1
read-write
0
Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1).
#0
1
Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 13 (if M = 1, SBNS = 1).
#1
LBKDIF
LIN Break Detect Interrupt Flag
7
1
read-write
0
No LIN break character has been detected.
#0
1
LIN break character has been detected.
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle waiting for a start bit.
#0
1
UART receiver active (RxD input not idle).
#1
RESERVED
no description available
5
1
read-only
RWUID
Receive Wake Up Idle Detect
3
1
read-write
0
During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.
#0
1
During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data not inverted.
#0
1
Receive data inverted.
#1
WDOG
Watchdog timer
WDOG
0x0
0x0
0x8
registers
n
WDOG_EWM
28
INT_Watchdog
28
CNT
Watchdog Counter Register.
WDOG
0x2
16
read-write
n
0x0
0x0
CNT
Watchdog Counter Value
0
16
read-write
CNTH
Watchdog Counter Register: High
WDOG
0x2
8
read-only
n
0x0
0x0
CNTHIGH
High byte of the Watchdog Counter
0
8
read-only
CNTL
Watchdog Counter Register: Low
0x3
8
read-only
n
0x0
0x0
CNTLOW
Low byte of the Watchdog Counter
0
8
read-only
CS1
Watchdog Control and Status Register 1
0x0
8
read-write
n
0x0
0x0
DBG
Debug Enable
2
1
read-write
0
Watchdog disabled in chip debug mode.
#0
1
Watchdog enabled in chip debug mode.
#1
EN
Watchdog Enable
7
1
read-write
0
Watchdog disabled.
#0
1
Watchdog enabled.
#1
INT
Watchdog Interrupt
6
1
read-write
0
Watchdog interrupts are disabled. Watchdog resets are not delayed.
#0
1
Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks.
#1
STOP
Stop Enable
0
1
read-write
0
Watchdog disabled in chip stop mode.
#0
1
Watchdog enabled in chip stop mode.
#1
TST
Watchdog Test
3
2
read-write
00
Watchdog test mode disabled.
#00
01
Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode.
#01
10
Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL.
#10
11
Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH.
#11
UPDATE
Allow updates
5
1
read-write
0
Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
#0
1
Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence.
#1
WAIT
Wait Enable
1
1
read-write
0
Watchdog disabled in chip wait mode.
#0
1
Watchdog enabled in chip wait mode.
#1
CS2
Watchdog Control and Status Register 2
0x1
8
read-write
n
0x0
0x0
CLK
Watchdog Clock
0
2
read-write
00
Bus clock.
#00
01
1 kHz internal low-power oscillator (LPOCLK).
#01
10
32 kHz internal oscillator (ICSIRCLK).
#10
11
External clock source.
#11
FLG
Watchdog Interrupt Flag
6
1
read-write
0
No interrupt occurred.
#0
1
An interrupt occurred.
#1
PRES
Watchdog Prescalar
4
1
read-write
0
256 prescalar disabled.
#0
1
256 prescalar enabled.
#1
RESERVED
no description available
2
2
read-only
RESERVED
no description available
5
1
read-only
WIN
Watchdog Window
7
1
read-write
0
Window mode disabled.
#0
1
Window mode enabled.
#1
TOVAL
Watchdog Timeout Value Register.
WDOG
0x4
16
read-write
n
0x0
0x0
TOVAL
Watchdog Timeout Value
0
16
read-write
TOVALH
Watchdog Timeout Value Register: High
WDOG
0x4
8
read-write
n
0x0
0x0
TOVALHIGH
High byte of the timeout value
0
8
read-write
TOVALL
Watchdog Timeout Value Register: Low
0x5
8
read-write
n
0x0
0x0
TOVALLOW
Low byte of the timeout value
0
8
read-write
WIN
Watchdog Window Register.
WDOG
0x6
16
read-write
n
0x0
0x0
WIN
Watchdog Window Value
0
16
read-write
WINH
Watchdog Window Register: High
WDOG
0x6
8
read-write
n
0x0
0x0
WINHIGH
High byte of Watchdog Window
0
8
read-write
WINL
Watchdog Window Register: Low
0x7
8
read-write
n
0x0
0x0
WINLOW
Low byte of Watchdog Window
0
8
read-write